From c19491894d4baf2155387e48aa326e1b52d7b986 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 17 Jun 2022 14:28:07 +0300 Subject: [PATCH] drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order Starting with TGL the disabling order of HDMI transcoder clock vs. DDI BUF has swapped, fix this. There hasn't been any issues seen related to this, but let's follow the spec. Reported-by: Sandeep K Lakkakula Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal Link: https://patchwork.freedesktop.org/patch/msgid/20220617112807.1586621-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f76eb6e345ec..ec131973f374 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2691,10 +2691,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); - intel_ddi_disable_pipe_clock(old_crtc_state); + if (DISPLAY_VER(dev_priv) < 12) + intel_ddi_disable_pipe_clock(old_crtc_state); intel_disable_ddi_buf(encoder, old_crtc_state); + if (DISPLAY_VER(dev_priv) >= 12) + intel_ddi_disable_pipe_clock(old_crtc_state); + intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain, fetch_and_zero(&dig_port->ddi_io_wakeref));