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drm/amd/pp: Delete unnecessary function argument
in populate_single_graphic_level for smu7 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
c7429b3ae9
commit
c1f2fb6b63
5 changed files with 8 additions and 18 deletions
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@ -411,8 +411,7 @@ static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,
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}
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static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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uint32_t clock, uint16_t sclk_al_threshold,
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struct SMU7_Discrete_GraphicsLevel *level)
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uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)
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{
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int result;
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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@ -438,7 +437,7 @@ static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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clock,
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&level->MinVddcPhases);
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level->ActivityLevel = sclk_al_threshold;
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level->ActivityLevel = data->current_profile_setting.sclk_activity;
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level->CcPwrDynRm = 0;
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level->CcPwrDynRm1 = 0;
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level->EnabledForActivity = 0;
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@ -492,7 +491,6 @@ static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = ci_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->current_profile_setting.sclk_activity,
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&levels[i]);
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if (result)
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return result;
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@ -968,8 +968,7 @@ static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
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}
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static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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uint32_t clock, uint16_t sclk_al_threshold,
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struct SMU73_Discrete_GraphicsLevel *level)
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uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)
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{
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int result;
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/* PP_Clocks minClocks; */
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@ -996,7 +995,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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return result);
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level->SclkFrequency = clock;
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level->ActivityLevel = sclk_al_threshold;
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level->ActivityLevel = data->current_profile_setting.sclk_activity;
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level->CcPwrDynRm = 0;
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level->CcPwrDynRm1 = 0;
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level->EnabledForActivity = 0;
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@ -1059,7 +1058,6 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = fiji_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->current_profile_setting.sclk_activity,
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&levels[i]);
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if (result)
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return result;
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@ -894,7 +894,6 @@ static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
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static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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uint32_t engine_clock,
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uint16_t sclk_activity_level_threshold,
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SMU71_Discrete_GraphicsLevel *graphic_level)
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{
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int result;
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@ -920,7 +919,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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&graphic_level->MinVddcPhases);
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/* Indicates maximum activity level for this performance level. 50% for now*/
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graphic_level->ActivityLevel = sclk_activity_level_threshold;
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graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
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graphic_level->CcPwrDynRm = 0;
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graphic_level->CcPwrDynRm1 = 0;
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@ -985,7 +984,6 @@ static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = iceland_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->current_profile_setting.sclk_activity,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result != 0)
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return result;
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@ -934,8 +934,7 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
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}
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static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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uint32_t clock, uint16_t sclk_al_threshold,
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struct SMU74_Discrete_GraphicsLevel *level)
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uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
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{
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int result;
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/* PP_Clocks minClocks; */
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@ -962,7 +961,7 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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"can not find VDDC voltage value for "
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"VDDC engine clock dependency table",
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return result);
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level->ActivityLevel = sclk_al_threshold;
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level->ActivityLevel = data->current_profile_setting.sclk_activity;
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level->CcPwrDynRm = 0;
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level->CcPwrDynRm1 = 0;
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@ -1033,7 +1032,6 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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result = polaris10_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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hw_data->current_profile_setting.sclk_activity,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result)
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return result;
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@ -608,7 +608,6 @@ static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
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static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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uint32_t engine_clock,
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uint16_t sclk_activity_level_threshold,
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SMU72_Discrete_GraphicsLevel *graphic_level)
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{
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int result;
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@ -636,7 +635,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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/* SCLK frequency in units of 10KHz*/
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graphic_level->SclkFrequency = engine_clock;
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/* Indicates maximum activity level for this performance level. 50% for now*/
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graphic_level->ActivityLevel = sclk_activity_level_threshold;
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graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
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graphic_level->CcPwrDynRm = 0;
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graphic_level->CcPwrDynRm1 = 0;
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@ -704,7 +703,6 @@ static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = tonga_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->current_profile_setting.sclk_activity,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result != 0)
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return result;
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