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OMAP2: PRCM: fix some SHIFT macros that were actually bitmasks
After Charu's GPIO hwmod patches, GPIO initialization on N800 emits the following messages for all GPIO banks: omap_hwmod: gpio1: cannot be enabled (3) This is due to OMAP24XX_ST_GPIOS_SHIFT being defined as a bitmask. Fix this and also fix two other macros that had the same problem. Thanks to Tony Lindgren <tony@atomide.com> for originally reporting this bug. Signed-off-by: Paul Walmsley <paul@pwsan.com Cc: Charulatha Varadarajan <charu@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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1 changed files with 6 additions and 5 deletions
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@ -243,13 +243,14 @@
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#define OMAP24XX_EN_GPT1_MASK (1 << 0)
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/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
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#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
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#define OMAP24XX_ST_GPIOS_MASK 2
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#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
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#define OMAP24XX_ST_GPT1_MASK 0
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#define OMAP24XX_ST_GPIOS_SHIFT 2
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#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
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#define OMAP24XX_ST_GPT1_SHIFT 0
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#define OMAP24XX_ST_GPT1_MASK (1 << 0)
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/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
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#define OMAP2430_ST_MDM_SHIFT (1 << 0)
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#define OMAP2430_ST_MDM_SHIFT 0
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#define OMAP2430_ST_MDM_MASK (1 << 0)
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/* 3430 register bits shared between CM & PRM registers */
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