MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
The inline assembler used on 32-bit kernels was using the "h" constraint which was considered dangerous and removed for gcc 4.4.0. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
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bb86bf28ae
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c21004cd5b
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@ -6,105 +6,63 @@
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* License. See the file "COPYING" in the main directory of this archive
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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* for more details.
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*/
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*/
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#ifndef _ASM_DIV64_H
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#ifndef __ASM_DIV64_H
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#define _ASM_DIV64_H
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#define __ASM_DIV64_H
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#include <asm-generic/div64.h>
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#if BITS_PER_LONG == 64
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#include <linux/types.h>
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#include <linux/types.h>
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#if (_MIPS_SZLONG == 32)
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#include <asm/compiler.h>
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/*
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/*
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* No traps on overflows for any of these...
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* No traps on overflows for any of these...
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*/
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*/
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#define do_div64_32(res, high, low, base) ({ \
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#define __div64_32(n, base) \
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unsigned long __quot32, __mod32; \
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({ \
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unsigned long __cf, __tmp, __tmp2, __i; \
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unsigned long __cf, __tmp, __tmp2, __i; \
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\
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unsigned long __quot32, __mod32; \
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__asm__(".set push\n\t" \
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unsigned long __high, __low; \
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".set noat\n\t" \
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unsigned long long __n; \
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".set noreorder\n\t" \
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\
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"move %2, $0\n\t" \
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__high = *__n >> 32; \
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"move %3, $0\n\t" \
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__low = __n; \
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"b 1f\n\t" \
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__asm__( \
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" li %4, 0x21\n" \
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" .set push \n" \
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"0:\n\t" \
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" .set noat \n" \
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"sll $1, %0, 0x1\n\t" \
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" .set noreorder \n" \
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"srl %3, %0, 0x1f\n\t" \
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" move %2, $0 \n" \
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"or %0, $1, %5\n\t" \
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" move %3, $0 \n" \
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"sll %1, %1, 0x1\n\t" \
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" b 1f \n" \
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"sll %2, %2, 0x1\n" \
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" li %4, 0x21 \n" \
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"1:\n\t" \
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"0: \n" \
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"bnez %3, 2f\n\t" \
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" sll $1, %0, 0x1 \n" \
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" sltu %5, %0, %z6\n\t" \
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" srl %3, %0, 0x1f \n" \
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"bnez %5, 3f\n" \
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" or %0, $1, %5 \n" \
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"2:\n\t" \
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" sll %1, %1, 0x1 \n" \
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" addiu %4, %4, -1\n\t" \
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" sll %2, %2, 0x1 \n" \
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"subu %0, %0, %z6\n\t" \
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"1: \n" \
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"addiu %2, %2, 1\n" \
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" bnez %3, 2f \n" \
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"3:\n\t" \
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" sltu %5, %0, %z6 \n" \
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"bnez %4, 0b\n\t" \
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" bnez %5, 3f \n" \
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" srl %5, %1, 0x1f\n\t" \
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"2: \n" \
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".set pop" \
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" addiu %4, %4, -1 \n" \
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: "=&r" (__mod32), "=&r" (__tmp), \
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" subu %0, %0, %z6 \n" \
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"=&r" (__quot32), "=&r" (__cf), \
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" addiu %2, %2, 1 \n" \
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"=&r" (__i), "=&r" (__tmp2) \
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"3: \n" \
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: "Jr" (base), "0" (high), "1" (low)); \
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" bnez %4, 0b\n\t" \
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\
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" srl %5, %1, 0x1f\n\t" \
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(res) = __quot32; \
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" .set pop" \
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__mod32; })
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: "=&r" (__mod32), "=&r" (__tmp), \
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"=&r" (__quot32), "=&r" (__cf), \
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"=&r" (__i), "=&r" (__tmp2) \
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: "Jr" (base), "0" (__high), "1" (__low)); \
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\
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(__n) = __quot32; \
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__mod32; \
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})
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#define do_div(n, base) ({ \
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#endif /* BITS_PER_LONG == 64 */
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unsigned long long __quot; \
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unsigned long __mod; \
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unsigned long long __div; \
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unsigned long __upper, __low, __high, __base; \
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\
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__div = (n); \
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__base = (base); \
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\
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__high = __div >> 32; \
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__low = __div; \
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__upper = __high; \
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\
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if (__high) \
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__asm__("divu $0, %z2, %z3" \
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: "=h" (__upper), "=l" (__high) \
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: "Jr" (__high), "Jr" (__base) \
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: GCC_REG_ACCUM); \
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\
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__mod = do_div64_32(__low, __upper, __low, __base); \
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\
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__quot = __high; \
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__quot = __quot << 32 | __low; \
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(n) = __quot; \
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__mod; })
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#endif /* (_MIPS_SZLONG == 32) */
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#endif /* __ASM_DIV64_H */
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#if (_MIPS_SZLONG == 64)
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/*
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* Hey, we're already 64-bit, no
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* need to play games..
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*/
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#define do_div(n, base) ({ \
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unsigned long __quot; \
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unsigned int __mod; \
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unsigned long __div; \
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unsigned int __base; \
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\
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__div = (n); \
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__base = (base); \
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\
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__mod = __div % __base; \
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__quot = __div / __base; \
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\
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(n) = __quot; \
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__mod; })
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#endif /* (_MIPS_SZLONG == 64) */
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#endif /* _ASM_DIV64_H */
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