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[MIPS] TX49 MFC0 bug workaround
If mfc0 $12 follows store and the mfc0 is last instruction of a page and fetching the next instruction causes TLB miss, the result of the mfc0 might wrongly contain EXL bit. ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 Workaround: mask EXL bit of the result or place a nop before mfc0. It doesn't harm to always clear those bits, so we change the code to do so. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 17 additions and 6 deletions
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@ -47,6 +47,17 @@ static inline void local_irq_enable(void)
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* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
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* no nops at all.
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*/
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/*
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* For TX49, operating only IE bit is not enough.
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*
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* If mfc0 $12 follows store and the mfc0 is last instruction of a
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* page and fetching the next instruction causes TLB miss, the result
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* of the mfc0 might wrongly contain EXL bit.
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*
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* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
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*
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* Workaround: mask EXL bit of the result or place a nop before mfc0.
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*/
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__asm__ (
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" .macro local_irq_disable\n"
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" .set push \n"
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@ -55,8 +66,8 @@ __asm__ (
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" di \n"
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#else
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" mfc0 $1,$12 \n"
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" ori $1,1 \n"
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" xori $1,1 \n"
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" ori $1,0x1f \n"
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" xori $1,0x1f \n"
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" .set noreorder \n"
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" mtc0 $1,$12 \n"
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#endif
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@ -96,8 +107,8 @@ __asm__ (
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" andi \\result, 1 \n"
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#else
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" mfc0 \\result, $12 \n"
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" ori $1, \\result, 1 \n"
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" xori $1, 1 \n"
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" ori $1, \\result, 0x1f \n"
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" xori $1, 0x1f \n"
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" .set noreorder \n"
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" mtc0 $1, $12 \n"
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#endif
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@ -136,8 +147,8 @@ __asm__ (
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#else
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" mfc0 $1, $12 \n"
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" andi \\flags, 1 \n"
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" ori $1, 1 \n"
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" xori $1, 1 \n"
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" ori $1, 0x1f \n"
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" xori $1, 0x1f \n"
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" or \\flags, $1 \n"
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" mtc0 \\flags, $12 \n"
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#endif
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