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ARM: dts: mx53qsb: Add support for parallel display
Add support for CLAA WVGA display for i.MX53 QSB. Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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2 changed files with 62 additions and 0 deletions
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@ -21,6 +21,33 @@ memory {
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reg = <0x70000000 0x40000000>;
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reg = <0x70000000 0x40000000>;
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};
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};
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display@di0 {
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compatible = "fsl,imx-parallel-display";
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crtcs = <&ipu 0>;
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interface-pix-fmt = "rgb565";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp0_1>;
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status = "disabled";
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display-timings {
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claawvga {
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native-mode;
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clock-frequency = <27000000>;
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hactive = <800>;
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vactive = <480>;
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hback-porch = <40>;
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hfront-porch = <60>;
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vback-porch = <10>;
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vfront-porch = <10>;
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hsync-len = <20>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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gpio-keys {
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gpio-keys {
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compatible = "gpio-keys";
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compatible = "gpio-keys";
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@ -544,6 +544,41 @@ MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
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};
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};
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};
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};
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ipu_disp0 {
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pinctrl_ipu_disp0_1: ipudisp0grp-1 {
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fsl,pins = <
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MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
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MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
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MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
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MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
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MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
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MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
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MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
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MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
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MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
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MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
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MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
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MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
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MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
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MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
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MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
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MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
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MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
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MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
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MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
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MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
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MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
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MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
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MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
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MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
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MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
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MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
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MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
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MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
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>;
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};
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};
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ipu_disp1 {
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ipu_disp1 {
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pinctrl_ipu_disp1_1: ipudisp1grp-1 {
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pinctrl_ipu_disp1_1: ipudisp1grp-1 {
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fsl,pins = <
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fsl,pins = <
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