drm/i915/display: remove explicit CNL handling from intel_display_power.c
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in intel_display_power.c. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-14-lucas.demarchi@intel.com
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c988d2dcd2
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c27310e3d6
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@ -448,17 +448,6 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
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hsw_wait_for_power_well_enable(dev_priv, power_well, false);
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/* Display WA #1178: cnl */
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if (IS_CANNONLAKE(dev_priv) &&
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pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
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pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
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u32 val;
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val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
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val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
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intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
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}
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if (power_well->desc->hsw.has_fuses) {
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enum skl_power_gate pg;
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@ -2744,63 +2733,6 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
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BIT_ULL(POWER_DOMAIN_GMBUS) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
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BIT_ULL(POWER_DOMAIN_PIPE_B) | \
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BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
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BIT_ULL(POWER_DOMAIN_PIPE_C) | \
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BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
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BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
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BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
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BIT_ULL(POWER_DOMAIN_AUX_B) | \
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BIT_ULL(POWER_DOMAIN_AUX_C) | \
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BIT_ULL(POWER_DOMAIN_AUX_D) | \
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BIT_ULL(POWER_DOMAIN_AUX_F) | \
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BIT_ULL(POWER_DOMAIN_AUDIO) | \
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BIT_ULL(POWER_DOMAIN_VGA) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_AUX_A) | \
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BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_AUX_B) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_AUX_C) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_AUX_D) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_AUX_F) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
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BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
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CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
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BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
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BIT_ULL(POWER_DOMAIN_MODESET) | \
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BIT_ULL(POWER_DOMAIN_AUX_A) | \
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BIT_ULL(POWER_DOMAIN_INIT))
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/*
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* ICL PW_0/PG_0 domains (HW/DMC control):
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* - PCI
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@ -3707,148 +3639,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
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},
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};
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static const struct i915_power_well_desc cnl_power_wells[] = {
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{
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.name = "always-on",
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.always_on = true,
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.domains = POWER_DOMAIN_MASK,
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.ops = &i9xx_always_on_power_well_ops,
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.id = DISP_PW_ID_NONE,
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},
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{
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.name = "power well 1",
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/* Handled by the DMC firmware */
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.always_on = true,
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.domains = 0,
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.ops = &hsw_power_well_ops,
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.id = SKL_DISP_PW_1,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = SKL_PW_CTL_IDX_PW_1,
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.hsw.has_fuses = true,
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},
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},
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{
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.name = "AUX A",
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.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
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},
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},
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{
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.name = "AUX B",
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.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
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},
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},
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{
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.name = "AUX C",
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.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
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},
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},
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{
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.name = "AUX D",
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.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = CNL_PW_CTL_IDX_AUX_D,
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},
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},
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{
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.name = "DC off",
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.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
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.ops = &gen9_dc_off_power_well_ops,
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.id = SKL_DISP_DC_OFF,
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},
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{
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.name = "power well 2",
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.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = SKL_DISP_PW_2,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = SKL_PW_CTL_IDX_PW_2,
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.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
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.hsw.has_vga = true,
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.hsw.has_fuses = true,
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},
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},
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{
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.name = "DDI A IO power well",
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.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
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},
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},
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{
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.name = "DDI B IO power well",
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.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
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},
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},
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{
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.name = "DDI C IO power well",
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.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
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},
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},
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{
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.name = "DDI D IO power well",
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.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = DISP_PW_ID_NONE,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
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},
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},
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{
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.name = "DDI F IO power well",
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.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = CNL_DISP_PW_DDI_F_IO,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
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},
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},
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{
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.name = "AUX F",
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.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
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.ops = &hsw_power_well_ops,
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.id = CNL_DISP_PW_DDI_F_AUX,
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{
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.hsw.regs = &hsw_power_well_regs,
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.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
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},
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},
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};
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static const struct i915_power_well_ops icl_aux_power_well_ops = {
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.sync_hw = hsw_power_well_sync_hw,
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.enable = icl_aux_power_well_enable,
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@ -5148,12 +4938,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
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err = set_power_wells(power_domains, tgl_power_wells);
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} else if (DISPLAY_VER(dev_priv) == 11) {
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err = set_power_wells(power_domains, icl_power_wells);
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} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
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err = set_power_wells(power_domains, cnl_power_wells);
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} else if (IS_CANNONLAKE(dev_priv)) {
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err = set_power_wells_mask(power_domains, cnl_power_wells,
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BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
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BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
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} else if (IS_GEMINILAKE(dev_priv)) {
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err = set_power_wells(power_domains, glk_power_wells);
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} else if (IS_BROXTON(dev_priv)) {
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@ -5708,75 +5492,6 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
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usleep_range(10, 30); /* 10 us delay per Bspec */
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}
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static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
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{
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struct i915_power_domains *power_domains = &dev_priv->power_domains;
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struct i915_power_well *well;
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gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
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/* 1. Enable PCH Reset Handshake */
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intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
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if (!HAS_DISPLAY(dev_priv))
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return;
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/* 2-3. */
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intel_combo_phy_init(dev_priv);
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/*
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* 4. Enable Power Well 1 (PG1).
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* The AUX IO power wells will be enabled on demand.
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*/
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mutex_lock(&power_domains->lock);
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well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
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intel_power_well_enable(dev_priv, well);
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mutex_unlock(&power_domains->lock);
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/* 5. Enable CD clock */
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intel_cdclk_init_hw(dev_priv);
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/* 6. Enable DBUF */
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gen9_dbuf_enable(dev_priv);
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if (resume && intel_dmc_has_payload(dev_priv))
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intel_dmc_load_program(dev_priv);
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}
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static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
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{
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struct i915_power_domains *power_domains = &dev_priv->power_domains;
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struct i915_power_well *well;
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if (!HAS_DISPLAY(dev_priv))
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return;
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gen9_disable_dc_states(dev_priv);
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/* 1. Disable all display engine functions -> aready done */
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/* 2. Disable DBUF */
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gen9_dbuf_disable(dev_priv);
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/* 3. Disable CD clock */
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intel_cdclk_uninit_hw(dev_priv);
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/*
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* 4. Disable Power Well 1 (PG1).
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* The AUX IO power wells are toggled on demand, so they are already
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* disabled at this point.
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*/
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mutex_lock(&power_domains->lock);
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well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
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intel_power_well_disable(dev_priv, well);
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mutex_unlock(&power_domains->lock);
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usleep_range(10, 30); /* 10 us delay per Bspec */
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/* 5. */
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intel_combo_phy_uninit(dev_priv);
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}
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struct buddy_page_mask {
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u32 page_mask;
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u8 type;
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@ -6125,8 +5840,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
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if (DISPLAY_VER(i915) >= 11) {
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icl_display_core_init(i915, resume);
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} else if (IS_CANNONLAKE(i915)) {
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cnl_display_core_init(i915, resume);
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} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
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bxt_display_core_init(i915, resume);
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} else if (DISPLAY_VER(i915) == 9) {
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@ -6286,8 +5999,6 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
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if (DISPLAY_VER(i915) >= 11)
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icl_display_core_uninit(i915);
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else if (IS_CANNONLAKE(i915))
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cnl_display_core_uninit(i915);
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else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
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bxt_display_core_uninit(i915);
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else if (DISPLAY_VER(i915) == 9)
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@ -142,8 +142,6 @@ enum i915_power_well_id {
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SKL_DISP_PW_MISC_IO,
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SKL_DISP_PW_1,
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SKL_DISP_PW_2,
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CNL_DISP_PW_DDI_F_IO,
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CNL_DISP_PW_DDI_F_AUX,
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ICL_DISP_PW_3,
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SKL_DISP_DC_OFF,
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TGL_DISP_PW_TC_COLD_OFF,
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@ -9890,19 +9890,6 @@ enum skl_power_gate {
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((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
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#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
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#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
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#define _CNL_AUX_ANAOVRD1_B 0x162250
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#define _CNL_AUX_ANAOVRD1_C 0x162210
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#define _CNL_AUX_ANAOVRD1_D 0x1622D0
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#define _CNL_AUX_ANAOVRD1_F 0x162A90
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#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
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_CNL_AUX_ANAOVRD1_B, \
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_CNL_AUX_ANAOVRD1_C, \
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_CNL_AUX_ANAOVRD1_D, \
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_CNL_AUX_ANAOVRD1_F))
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#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
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#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
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#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
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#define _ICL_AUX_ANAOVRD1_A 0x162398
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#define _ICL_AUX_ANAOVRD1_B 0x6C398
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