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x86/trampoline: Bypass compat mode in trampoline_start64() if not needed 

The trampoline_start64() vector is used when a secondary CPU starts in
64-bit mode. The current implementation directly enters compatibility
mode. It is necessary to disable paging and re-enable it in the correct
paging mode: either 4- or 5-level, depending on the configuration.

The X86S[1] ISA does not support compatibility mode in ring 0, and
paging cannot be disabled.

Rework the trampoline_start64() function to only enter compatibility
mode if it is necessary to change the paging mode. If the CPU is
already in the desired paging mode, proceed in long mode.

This allows a secondary CPU to boot on an X86S machine as long as the
CPU is already in the correct paging mode.

In the future, there will be a mechanism to switch between paging modes
without disabling paging.

[1] https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html

[ dhansen: changelog tweaks ]

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Link: https://lore.kernel.org/all/20240126100101.689090-1-kirill.shutemov%40linux.intel.com
This commit is contained in:
Kirill A. Shutemov 2024-01-26 12:01:01 +02:00 committed by Dave Hansen
parent 43b1d3e68e
commit c2cfc23f79
1 changed files with 32 additions and 1 deletions
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33
arch/x86/realmode/rm/trampoline_64.S
View File

@ -37,13 +37,15 @@
.text
.code16
.macro LOCK_AND_LOAD_REALMODE_ESP lock_pa=0
.macro LOCK_AND_LOAD_REALMODE_ESP lock_pa=0 lock_rip=0
/*
* Make sure only one CPU fiddles with the realmode stack
*/
.Llock_rm\@:
.if \lock_pa
lock btsl $0, pa_tr_lock
.elseif \lock_rip
lock btsl $0, tr_lock(%rip)
.else
lock btsl $0, tr_lock
.endif
@ -220,6 +222,35 @@ SYM_CODE_START(trampoline_start64)
lidt tr_idt(%rip)
lgdt tr_gdt64(%rip)
/* Check if paging mode has to be changed */
movq %cr4, %rax
xorl tr_cr4(%rip), %eax
testl $X86_CR4_LA57, %eax
jnz .L_switch_paging
/* Paging mode is correct proceed in 64-bit mode */
LOCK_AND_LOAD_REALMODE_ESP lock_rip=1
movw $__KERNEL_DS, %dx
movl %edx, %ss
addl $pa_real_mode_base, %esp
movl %edx, %ds
movl %edx, %es
movl %edx, %fs
movl %edx, %gs
movl $pa_trampoline_pgd, %eax
movq %rax, %cr3
pushq $__KERNEL_CS
pushq tr_start(%rip)
lretq
.L_switch_paging:
/*
* To switch between 4- and 5-level paging modes, it is necessary
* to disable paging. This must be done in the compatibility mode.
*/
ljmpl *tr_compat(%rip)
SYM_CODE_END(trampoline_start64)