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KVM: MIPS: Document MIPS specifics of KVM API.
Document the MIPS specific parts of the KVM API, including: - The layout of the kvm_regs structure. - The interrupt number passed to KVM_INTERRUPT. - The registers supported by the KVM_{GET,SET}_ONE_REG interface, and the encoding of those register ids. - That KVM_INTERRUPT and KVM_GET_REG_LIST are supported on MIPS. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: Randy Dunlap <rdunlap@infradead.org> Cc: linux-doc@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -297,6 +297,15 @@ struct kvm_regs {
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__u64 rip, rflags;
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};
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/* mips */
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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__u64 gpr[32];
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__u64 hi;
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__u64 lo;
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__u64 pc;
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};
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4.12 KVM_SET_REGS
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@ -378,7 +387,7 @@ struct kvm_translation {
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4.16 KVM_INTERRUPT
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Capability: basic
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Architectures: x86, ppc
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Architectures: x86, ppc, mips
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Type: vcpu ioctl
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Parameters: struct kvm_interrupt (in)
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Returns: 0 on success, -1 on error
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@ -423,6 +432,11 @@ c) KVM_INTERRUPT_SET_LEVEL
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Note that any value for 'irq' other than the ones stated above is invalid
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and incurs unexpected behavior.
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MIPS:
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Queues an external interrupt to be injected into the virtual CPU. A negative
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interrupt number dequeues the interrupt.
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4.17 KVM_DEBUG_GUEST
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@ -1890,6 +1904,35 @@ registers, find a list below:
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PPC | KVM_REG_PPC_TM_VSCR | 32
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PPC | KVM_REG_PPC_TM_DSCR | 64
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PPC | KVM_REG_PPC_TM_TAR | 64
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MIPS | KVM_REG_MIPS_R0 | 64
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...
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MIPS | KVM_REG_MIPS_R31 | 64
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MIPS | KVM_REG_MIPS_HI | 64
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MIPS | KVM_REG_MIPS_LO | 64
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MIPS | KVM_REG_MIPS_PC | 64
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MIPS | KVM_REG_MIPS_CP0_INDEX | 32
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MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
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MIPS | KVM_REG_MIPS_CP0_USERLOCAL | 64
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MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
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MIPS | KVM_REG_MIPS_CP0_WIRED | 32
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MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
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MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
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MIPS | KVM_REG_MIPS_CP0_COUNT | 32
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MIPS | KVM_REG_MIPS_CP0_ENTRYHI | 64
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MIPS | KVM_REG_MIPS_CP0_COMPARE | 32
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MIPS | KVM_REG_MIPS_CP0_STATUS | 32
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MIPS | KVM_REG_MIPS_CP0_CAUSE | 32
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MIPS | KVM_REG_MIPS_CP0_EPC | 64
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MIPS | KVM_REG_MIPS_CP0_CONFIG | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG1 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG2 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG3 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG7 | 32
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MIPS | KVM_REG_MIPS_CP0_ERROREPC | 64
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MIPS | KVM_REG_MIPS_COUNT_CTL | 64
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MIPS | KVM_REG_MIPS_COUNT_RESUME | 64
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MIPS | KVM_REG_MIPS_COUNT_HZ | 64
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ARM registers are mapped using the lower 32 bits. The upper 16 of that
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is the register group type, or coprocessor number:
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@ -1928,6 +1971,22 @@ arm64 CCSIDR registers are demultiplexed by CSSELR value:
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arm64 system registers have the following id bit patterns:
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0x6030 0000 0013 <op0:2> <op1:3> <crn:4> <crm:4> <op2:3>
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MIPS registers are mapped using the lower 32 bits. The upper 16 of that is
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the register group type:
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MIPS core registers (see above) have the following id bit patterns:
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0x7030 0000 0000 <reg:16>
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MIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit
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patterns depending on whether they're 32-bit or 64-bit registers:
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0x7020 0000 0001 00 <reg:5> <sel:3> (32-bit)
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0x7030 0000 0001 00 <reg:5> <sel:3> (64-bit)
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MIPS KVM control registers (see above) have the following id bit patterns:
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0x7030 0000 0002 <reg:16>
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4.69 KVM_GET_ONE_REG
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Capability: KVM_CAP_ONE_REG
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@ -2415,7 +2474,7 @@ in VCPU matching underlying host.
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4.84 KVM_GET_REG_LIST
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Capability: basic
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Architectures: arm, arm64
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Architectures: arm, arm64, mips
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Type: vcpu ioctl
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Parameters: struct kvm_reg_list (in/out)
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Returns: 0 on success; -1 on error
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