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ASoC: mxs-saif: fix clock prepare and enable unbalance issue
Currently we directly call a clock_enable in trigger function without a clk_prepare as pair first. This will cause system hang immediately when run capture because the clock was not prepared(playback does not hang because the clock was prepared already by get_mclk before), a warning message in clock framework may cause a deadlock to reclaim clock lock (see: pl011_console_write). Here we prepare clock first in hw_param, then enable it in trigger function to guarantee the balance. Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -394,9 +394,14 @@ static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
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struct mxs_saif *master_saif;
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u32 scr, stat;
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int ret;
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master_saif = mxs_saif_get_master(saif);
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if (!master_saif)
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return -EINVAL;
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/* mclk should already be set */
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if (!saif->mclk && saif->mclk_in_use) {
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dev_err(cpu_dai->dev, "set mclk first\n");
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@ -420,6 +425,11 @@ static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
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return ret;
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}
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/* prepare clk in hw_param, enable in trigger */
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clk_prepare(saif->clk);
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if (saif != master_saif)
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clk_prepare(master_saif->clk);
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scr = __raw_readl(saif->base + SAIF_CTRL);
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scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
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