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iommu/vt-d: Fix dev iotlb pfsid use
commit 1c48db4492
upstream.
PFSID should be used in the invalidation descriptor for flushing
device IOTLBs on SRIOV VFs.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: stable@vger.kernel.org
Cc: "Ashok Raj" <ashok.raj@intel.com>
Cc: "Lu Baolu" <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
eb58c40465
commit
c2ea292b13
3 changed files with 21 additions and 7 deletions
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@ -1336,8 +1336,8 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
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qi_submit_sync(&desc, iommu);
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qi_submit_sync(&desc, iommu);
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}
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}
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void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
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void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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u64 addr, unsigned mask)
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u16 qdep, u64 addr, unsigned mask)
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{
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{
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struct qi_desc desc;
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struct qi_desc desc;
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@ -1352,7 +1352,7 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
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qdep = 0;
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qdep = 0;
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desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
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desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
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QI_DIOTLB_TYPE;
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QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
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qi_submit_sync(&desc, iommu);
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qi_submit_sync(&desc, iommu);
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}
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}
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@ -1503,6 +1503,20 @@ static void iommu_enable_dev_iotlb(struct device_domain_info *info)
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return;
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return;
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pdev = to_pci_dev(info->dev);
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pdev = to_pci_dev(info->dev);
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/* For IOMMU that supports device IOTLB throttling (DIT), we assign
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* PFSID to the invalidation desc of a VF such that IOMMU HW can gauge
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* queue depth at PF level. If DIT is not set, PFSID will be treated as
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* reserved, which should be set to 0.
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*/
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if (!ecap_dit(info->iommu->ecap))
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info->pfsid = 0;
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else {
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struct pci_dev *pf_pdev;
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/* pdev will be returned if device is not a vf */
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pf_pdev = pci_physfn(pdev);
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info->pfsid = PCI_DEVID(pf_pdev->bus->number, pf_pdev->devfn);
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}
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#ifdef CONFIG_INTEL_IOMMU_SVM
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#ifdef CONFIG_INTEL_IOMMU_SVM
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/* The PCIe spec, in its wisdom, declares that the behaviour of
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/* The PCIe spec, in its wisdom, declares that the behaviour of
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@ -1568,7 +1582,8 @@ static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
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sid = info->bus << 8 | info->devfn;
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sid = info->bus << 8 | info->devfn;
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qdep = info->ats_qdep;
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qdep = info->ats_qdep;
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qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
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qi_flush_dev_iotlb(info->iommu, sid, info->pfsid,
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qdep, addr, mask);
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}
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}
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spin_unlock_irqrestore(&device_domain_lock, flags);
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spin_unlock_irqrestore(&device_domain_lock, flags);
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}
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}
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@ -453,9 +453,8 @@ extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
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u8 fm, u64 type);
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u8 fm, u64 type);
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extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
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extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
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unsigned int size_order, u64 type);
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unsigned int size_order, u64 type);
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extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
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extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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u64 addr, unsigned mask);
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u16 qdep, u64 addr, unsigned mask);
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extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
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extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
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extern int dmar_ir_support(void);
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extern int dmar_ir_support(void);
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