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mmc: sdhci-pci: Add support for HS200 tuning mode on AMD, eMMC-4.5.1
This patch adds support for HS200 tuning mode on AMD eMMC-4.5.1 Reviewed-by: Sen, Pankaj <Pankaj.Sen@amd.com> Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com> Reviewed-by: Agrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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8336bf68b5
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1 changed files with 91 additions and 3 deletions
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@ -865,6 +865,86 @@ enum amd_chipset_gen {
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AMD_CHIPSET_UNKNOWN,
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};
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/* AMD registers */
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#define AMD_SD_AUTO_PATTERN 0xB8
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#define AMD_MSLEEP_DURATION 4
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#define AMD_SD_MISC_CONTROL 0xD0
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#define AMD_MAX_TUNE_VALUE 0x0B
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#define AMD_AUTO_TUNE_SEL 0x10800
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#define AMD_FIFO_PTR 0x30
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#define AMD_BIT_MASK 0x1F
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static void amd_tuning_reset(struct sdhci_host *host)
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{
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unsigned int val;
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val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
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val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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val &= ~SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
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}
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static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
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{
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unsigned int val;
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pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
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val &= ~AMD_BIT_MASK;
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val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
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pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
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}
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static void amd_enable_manual_tuning(struct pci_dev *pdev)
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{
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unsigned int val;
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pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
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val |= AMD_FIFO_PTR;
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pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
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}
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static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct pci_dev *pdev = slot->chip->pdev;
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u8 valid_win = 0;
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u8 valid_win_max = 0;
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u8 valid_win_end = 0;
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u8 ctrl, tune_around;
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amd_tuning_reset(host);
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for (tune_around = 0; tune_around < 12; tune_around++) {
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amd_config_tuning_phase(pdev, tune_around);
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if (mmc_send_tuning(host->mmc, opcode, NULL)) {
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valid_win = 0;
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msleep(AMD_MSLEEP_DURATION);
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ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
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sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
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} else if (++valid_win > valid_win_max) {
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valid_win_max = valid_win;
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valid_win_end = tune_around;
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}
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}
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if (!valid_win_max) {
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dev_err(&pdev->dev, "no tuning point found\n");
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return -EIO;
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}
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amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
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amd_enable_manual_tuning(pdev);
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host->mmc->retune_period = 0;
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return 0;
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}
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static int amd_probe(struct sdhci_pci_chip *chip)
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{
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struct pci_dev *smbus_dev;
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@ -887,16 +967,24 @@ static int amd_probe(struct sdhci_pci_chip *chip)
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}
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}
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if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
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if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
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chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
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chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
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}
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return 0;
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}
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static const struct sdhci_ops amd_sdhci_pci_ops = {
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.set_clock = sdhci_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_pci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.platform_execute_tuning = amd_execute_tuning,
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};
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static const struct sdhci_pci_fixes sdhci_amd = {
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.probe = amd_probe,
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.ops = &amd_sdhci_pci_ops,
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};
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static const struct pci_device_id pci_ids[] = {
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