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[SCSI] qla2xxx: Remove RISC pause/release barriers during flash manipulation.
Remove unnecessary RISC pause/release barriers during ISP24xx flash manipulation. The ISP24xx can arbitrate flash access requests during RISC executions. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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06c22bd13f
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1 changed files with 0 additions and 34 deletions
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@ -468,21 +468,12 @@ qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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uint32_t dwords)
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{
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uint32_t i;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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/* Pause RISC. */
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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/* Dword reads to flash. */
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for (i = 0; i < dwords; i++, faddr++)
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dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
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flash_data_to_access_addr(faddr)));
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/* Release RISC pause. */
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WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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return dwptr;
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}
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@ -532,10 +523,6 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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ret = QLA_SUCCESS;
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/* Pause RISC. */
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
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DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
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ha->host_no, man_id, flash_id));
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@ -599,10 +586,6 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
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RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
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/* Release RISC pause. */
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WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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return ret;
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}
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@ -630,11 +613,6 @@ qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
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{
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uint32_t i;
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uint32_t *dwptr;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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/* Pause RISC. */
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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/* Dword reads to flash. */
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dwptr = (uint32_t *)buf;
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@ -642,10 +620,6 @@ qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
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dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
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nvram_data_to_access_addr(naddr)));
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/* Release RISC pause. */
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WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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return buf;
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}
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@ -690,10 +664,6 @@ qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
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ret = QLA_SUCCESS;
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/* Pause RISC. */
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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/* Enable flash write. */
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WRT_REG_DWORD(®->ctrl_status,
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RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
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@ -728,9 +698,5 @@ qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
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RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
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RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
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/* Release RISC pause. */
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WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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return ret;
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}
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