fixes/cleanups for rc1, non-desktop flags for VR
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Merge tag 'drm-for-v4.15-part2' of git://people.freedesktop.org/~airlied/linux
Pull more drm updates from Dave Airlie:
"Fixes/cleanups for rc1, non-desktop flags for VR
- remove the MSM dt-bindings file Rob managed to push in the previous
pull.
- add a property/edid quirk to denote HMD devices, I had these
hanging around for a few weeks and Keith had done some work on
them, they are fairly self contained and small, and only affect
people using HTC Vive VR headsets so far.
- amdgpu, tegra, tilcdc, fsl fixes
- some imx-drm cleanups I missed, these seemed pretty small, and no
reason to hold off.
I have one TTM regression fix (fixes bochs-vga in qemu) sitting
locally awaiting review I'll probably send that in a separate pull
request tomorrow"
* tag 'drm-for-v4.15-part2' of git://people.freedesktop.org/~airlied/linux: (33 commits)
dt-bindings: remove file that was added accidentally
drm/edid: quirk HTC vive headset as non-desktop. [v2]
drm/fb: add support for not enabling fbcon on non-desktop displays [v2]
drm: add connector info/property for non-desktop displays [v2]
drm/amdgpu: fix rmmod KCQ disable failed error
drm/amdgpu: fix kernel hang when starting VNC server
drm/amdgpu: don't skip attributes when powerplay is enabled
drm/amd/pp: fix typecast error in powerplay.
drm/tilcdc: Remove obsolete "ti,tilcdc,slave" dts binding support
drm/tegra: sor: Reimplement pad clock
Revert "drm/radeon: dont switch vt on suspend"
drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence
drm/amd/powerplay: fix unfreeze level smc message for smu7
drm/amdgpu:fix memleak
drm/amdgpu:fix memleak in takedown
drm/amd/pp: fix dpm randomly failed on Vega10
drm/amdgpu: set f_mapping on exported DMA-bufs
drm/amdgpu: Properly allocate VM invalidate eng v2
drm/fsl-dcu: enable IRQ before drm_atomic_helper_resume()
drm/fsl-dcu: avoid disabling pixel clock twice on suspend
...
This commit is contained in:
Linus Torvalds
commit
c353bfc6eb
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|
@ -129,7 +129,7 @@ Optional properties:
|
|||
|
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example:
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display@di0 {
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disp0 {
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compatible = "fsl,imx-parallel-display";
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edid = [edid-data];
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interface-pix-fmt = "rgb24";
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|
|
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@ -59,12 +59,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
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return false;
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}
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tmp = bios[0x18] | (bios[0x19] << 8);
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if (bios[tmp + 0x14] != 0x0) {
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DRM_INFO("Not an x86 BIOS ROM\n");
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return false;
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}
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bios_header_start = bios[0x48] | (bios[0x49] << 8);
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if (!bios_header_start) {
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DRM_INFO("Can't locate bios header\n");
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@ -1495,8 +1495,11 @@ out:
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memset(wait, 0, sizeof(*wait));
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wait->out.status = (r > 0);
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wait->out.first_signaled = first;
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/* set return value 0 to indicate success */
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r = array[first]->error;
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if (first < fence_count && array[first])
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r = array[first]->error;
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else
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r = 0;
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err_free_fence_array:
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for (i = 0; i < fence_count; i++)
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@ -1837,6 +1837,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
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adev->ip_blocks[i].status.hw = false;
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}
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
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amdgpu_ucode_fini_bo(adev);
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for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
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if (!adev->ip_blocks[i].status.sw)
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continue;
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@ -3261,9 +3264,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
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pm_pg_lock = (*pos >> 23) & 1;
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if (*pos & (1ULL << 62)) {
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se_bank = (*pos >> 24) & 0x3FF;
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sh_bank = (*pos >> 34) & 0x3FF;
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instance_bank = (*pos >> 44) & 0x3FF;
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se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
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sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
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instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
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if (se_bank == 0x3FF)
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se_bank = 0xFFFFFFFF;
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@ -3337,9 +3340,9 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
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pm_pg_lock = (*pos >> 23) & 1;
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if (*pos & (1ULL << 62)) {
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se_bank = (*pos >> 24) & 0x3FF;
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sh_bank = (*pos >> 34) & 0x3FF;
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instance_bank = (*pos >> 44) & 0x3FF;
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se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
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sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
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instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
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if (se_bank == 0x3FF)
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se_bank = 0xFFFFFFFF;
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@ -3687,12 +3690,12 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
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return -EINVAL;
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/* decode offset */
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offset = (*pos & 0x7F);
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se = ((*pos >> 7) & 0xFF);
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sh = ((*pos >> 15) & 0xFF);
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cu = ((*pos >> 23) & 0xFF);
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wave = ((*pos >> 31) & 0xFF);
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simd = ((*pos >> 37) & 0xFF);
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offset = (*pos & GENMASK_ULL(6, 0));
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se = (*pos & GENMASK_ULL(14, 7)) >> 7;
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sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
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cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
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wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
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simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
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/* switch to the specific se/sh/cu */
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mutex_lock(&adev->grbm_idx_mutex);
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@ -3737,14 +3740,14 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
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return -EINVAL;
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/* decode offset */
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offset = (*pos & 0xFFF); /* in dwords */
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se = ((*pos >> 12) & 0xFF);
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sh = ((*pos >> 20) & 0xFF);
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cu = ((*pos >> 28) & 0xFF);
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wave = ((*pos >> 36) & 0xFF);
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simd = ((*pos >> 44) & 0xFF);
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thread = ((*pos >> 52) & 0xFF);
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bank = ((*pos >> 60) & 1);
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offset = *pos & GENMASK_ULL(11, 0);
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se = (*pos & GENMASK_ULL(19, 12)) >> 12;
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sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
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cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
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wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
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simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
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thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
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bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
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data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
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if (!data)
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|
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@ -63,6 +63,11 @@ retry:
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flags, NULL, resv, 0, &bo);
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if (r) {
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if (r != -ERESTARTSYS) {
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if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
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flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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goto retry;
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}
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if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
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initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
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goto retry;
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@ -323,7 +328,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
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r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
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bo->tbo.ttm->pages);
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if (r)
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goto unlock_mmap_sem;
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goto release_object;
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r = amdgpu_bo_reserve(bo, true);
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if (r)
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@ -348,9 +353,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
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free_pages:
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release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
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unlock_mmap_sem:
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up_read(¤t->mm->mmap_sem);
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release_object:
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drm_gem_object_put_unlocked(gobj);
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@ -556,9 +558,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
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dev_err(&dev->pdev->dev,
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"va_address 0x%lX is in reserved area 0x%X\n",
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(unsigned long)args->va_address,
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AMDGPU_VA_RESERVED_SIZE);
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"va_address 0x%LX is in reserved area 0x%LX\n",
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args->va_address, AMDGPU_VA_RESERVED_SIZE);
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return -EINVAL;
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}
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@ -71,12 +71,6 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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spin_lock(&mgr->lock);
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if (!drm_mm_clean(&mgr->mm)) {
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spin_unlock(&mgr->lock);
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return -EBUSY;
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}
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drm_mm_takedown(&mgr->mm);
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spin_unlock(&mgr->lock);
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kfree(mgr);
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@ -946,6 +946,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
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struct amdgpu_device *adev = dev_get_drvdata(dev);
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umode_t effective_mode = attr->mode;
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/* no skipping for powerplay */
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if (adev->powerplay.cgs_device)
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return effective_mode;
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/* Skip limit attributes if DPM is not enabled */
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if (!adev->pm.dpm_enabled &&
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(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
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@ -164,9 +164,6 @@ static int amdgpu_pp_hw_fini(void *handle)
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ret = adev->powerplay.ip_funcs->hw_fini(
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adev->powerplay.pp_handle);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
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amdgpu_ucode_fini_bo(adev);
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return ret;
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}
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|
|
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@ -169,10 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
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int flags)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
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struct dma_buf *buf;
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if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
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bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
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return ERR_PTR(-EPERM);
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return drm_gem_prime_export(dev, gobj, flags);
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buf = drm_gem_prime_export(dev, gobj, flags);
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if (!IS_ERR(buf))
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buf->file->f_mapping = dev->anon_inode->i_mapping;
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return buf;
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}
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|
|
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|
@ -442,8 +442,6 @@ static int psp_hw_fini(void *handle)
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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return 0;
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|
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amdgpu_ucode_fini_bo(adev);
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psp_ring_destroy(psp, PSP_RING_TYPE__KM);
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|
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amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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|
|
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|||
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|
@ -94,7 +94,8 @@ struct amdgpu_bo_list_entry;
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#define AMDGPU_MMHUB 1
|
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|
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/* hardcode that limit for now */
|
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#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
|
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#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
|
||||
|
||||
/* max vmids dedicated for process */
|
||||
#define AMDGPU_VM_MAX_RESERVED_VMID 1
|
||||
|
||||
|
|
|
|||
|
|
@ -68,11 +68,6 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man)
|
|||
struct amdgpu_vram_mgr *mgr = man->priv;
|
||||
|
||||
spin_lock(&mgr->lock);
|
||||
if (!drm_mm_clean(&mgr->mm)) {
|
||||
spin_unlock(&mgr->lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
drm_mm_takedown(&mgr->mm);
|
||||
spin_unlock(&mgr->lock);
|
||||
kfree(mgr);
|
||||
|
|
|
|||
|
|
@ -4670,6 +4670,14 @@ static int gfx_v7_0_sw_fini(void *handle)
|
|||
gfx_v7_0_cp_compute_fini(adev);
|
||||
gfx_v7_0_rlc_fini(adev);
|
||||
gfx_v7_0_mec_fini(adev);
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
|
||||
&adev->gfx.rlc.clear_state_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cs_ptr);
|
||||
if (adev->gfx.rlc.cp_table_size) {
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
|
||||
&adev->gfx.rlc.cp_table_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cp_table_ptr);
|
||||
}
|
||||
gfx_v7_0_free_microcode(adev);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -2118,6 +2118,15 @@ static int gfx_v8_0_sw_fini(void *handle)
|
|||
|
||||
gfx_v8_0_mec_fini(adev);
|
||||
gfx_v8_0_rlc_fini(adev);
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
|
||||
&adev->gfx.rlc.clear_state_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cs_ptr);
|
||||
if ((adev->asic_type == CHIP_CARRIZO) ||
|
||||
(adev->asic_type == CHIP_STONEY)) {
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
|
||||
&adev->gfx.rlc.cp_table_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cp_table_ptr);
|
||||
}
|
||||
gfx_v8_0_free_microcode(adev);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -207,6 +207,12 @@ static const u32 golden_settings_gc_9_1_rv1[] =
|
|||
SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
|
||||
};
|
||||
|
||||
static const u32 golden_settings_gc_9_x_common[] =
|
||||
{
|
||||
SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
|
||||
SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
|
||||
};
|
||||
|
||||
#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
|
||||
#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
|
||||
|
||||
|
|
@ -242,6 +248,9 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
|
|||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
|
||||
(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
|
||||
}
|
||||
|
||||
static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
|
||||
|
|
@ -988,12 +997,22 @@ static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
|
|||
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
|
||||
}
|
||||
|
||||
static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
|
||||
uint32_t wave, uint32_t thread,
|
||||
uint32_t start, uint32_t size,
|
||||
uint32_t *dst)
|
||||
{
|
||||
wave_read_regs(
|
||||
adev, simd, wave, thread,
|
||||
start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
|
||||
}
|
||||
|
||||
static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
|
||||
.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
|
||||
.select_se_sh = &gfx_v9_0_select_se_sh,
|
||||
.read_wave_data = &gfx_v9_0_read_wave_data,
|
||||
.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
|
||||
.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
|
||||
};
|
||||
|
||||
static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
|
||||
|
|
@ -1449,6 +1468,14 @@ static int gfx_v9_0_sw_fini(void *handle)
|
|||
|
||||
gfx_v9_0_mec_fini(adev);
|
||||
gfx_v9_0_ngg_fini(adev);
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
|
||||
&adev->gfx.rlc.clear_state_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cs_ptr);
|
||||
if (adev->asic_type == CHIP_RAVEN) {
|
||||
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
|
||||
&adev->gfx.rlc.cp_table_gpu_addr,
|
||||
(void **)&adev->gfx.rlc.cp_table_ptr);
|
||||
}
|
||||
gfx_v9_0_free_microcode(adev);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -392,7 +392,16 @@ static int gmc_v9_0_early_init(void *handle)
|
|||
static int gmc_v9_0_late_init(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
|
||||
/*
|
||||
* The latest engine allocation on gfx9 is:
|
||||
* Engine 0, 1: idle
|
||||
* Engine 2, 3: firmware
|
||||
* Engine 4~13: amdgpu ring, subject to change when ring number changes
|
||||
* Engine 14~15: idle
|
||||
* Engine 16: kfd tlb invalidation
|
||||
* Engine 17: Gart flushes
|
||||
*/
|
||||
unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
|
||||
unsigned i;
|
||||
|
||||
for(i = 0; i < adev->num_rings; ++i) {
|
||||
|
|
@ -405,9 +414,9 @@ static int gmc_v9_0_late_init(void *handle)
|
|||
ring->funcs->vmhub);
|
||||
}
|
||||
|
||||
/* Engine 17 is used for GART flushes */
|
||||
/* Engine 16 is used for KFD and 17 for GART flushes */
|
||||
for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
|
||||
BUG_ON(vm_inv_eng[i] > 17);
|
||||
BUG_ON(vm_inv_eng[i] > 16);
|
||||
|
||||
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1486,7 +1486,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
|
|||
if (vddci_id_buf[i] == virtual_voltage_id) {
|
||||
for (j = 0; j < profile->ucLeakageBinNum; j++) {
|
||||
if (efuse_voltage_id <= leakage_bin[j]) {
|
||||
*vddci = vddci_buf[j * profile->ucElbVDDC_Num + i];
|
||||
*vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -830,9 +830,9 @@ static int init_over_drive_limits(
|
|||
const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock =
|
||||
le16_to_cpu(powerplay_table->ulMaxODEngineClock);
|
||||
le32_to_cpu(powerplay_table->ulMaxODEngineClock);
|
||||
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
|
||||
le16_to_cpu(powerplay_table->ulMaxODMemoryClock);
|
||||
le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
|
||||
|
||||
hwmgr->platform_descriptor.minOverdriveVDDC = 0;
|
||||
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
|
||||
|
|
|
|||
|
|
@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
|
|||
"Trying to Unfreeze MCLK DPM when DPM is disabled",
|
||||
);
|
||||
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
|
||||
PPSMC_MSG_SCLKDPM_UnfreezeLevel),
|
||||
PPSMC_MSG_MCLKDPM_UnfreezeLevel),
|
||||
"Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
|
||||
return -EINVAL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -753,6 +753,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
uint32_t config_telemetry = 0;
|
||||
struct pp_atomfwctrl_voltage_table vol_table;
|
||||
struct cgs_system_info sys_info = {0};
|
||||
uint32_t reg;
|
||||
|
||||
data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
|
||||
if (data == NULL)
|
||||
|
|
@ -859,6 +860,16 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
advanceFanControlParameters.usFanPWMMinLimit *
|
||||
hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
|
||||
|
||||
reg = soc15_get_register_offset(DF_HWID, 0,
|
||||
mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
|
||||
mmDF_CS_AON0_DramBaseAddress0);
|
||||
data->mem_channels = (cgs_read_register(hwmgr->device, reg) &
|
||||
DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
|
||||
DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
|
||||
PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
|
||||
"Mem Channel Index Exceeded maximum!",
|
||||
return -EINVAL);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -1777,7 +1788,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
|
|||
struct vega10_single_dpm_table *dpm_table =
|
||||
&(data->dpm_table.mem_table);
|
||||
int result = 0;
|
||||
uint32_t i, j, reg, mem_channels;
|
||||
uint32_t i, j;
|
||||
|
||||
for (i = 0; i < dpm_table->count; i++) {
|
||||
result = vega10_populate_single_memory_level(hwmgr,
|
||||
|
|
@ -1801,20 +1812,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
|
|||
i++;
|
||||
}
|
||||
|
||||
reg = soc15_get_register_offset(DF_HWID, 0,
|
||||
mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
|
||||
mmDF_CS_AON0_DramBaseAddress0);
|
||||
mem_channels = (cgs_read_register(hwmgr->device, reg) &
|
||||
DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
|
||||
DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
|
||||
PP_ASSERT_WITH_CODE(mem_channels < ARRAY_SIZE(channel_number),
|
||||
"Mem Channel Index Exceeded maximum!",
|
||||
return -1);
|
||||
|
||||
pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
|
||||
pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
|
||||
pp_table->MemoryChannelWidth =
|
||||
cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH *
|
||||
channel_number[mem_channels]);
|
||||
(uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
|
||||
channel_number[data->mem_channels]);
|
||||
|
||||
pp_table->LowestUclkReservedForUlv =
|
||||
(uint8_t)(data->lowest_uclk_reserved_for_ulv);
|
||||
|
|
|
|||
|
|
@ -389,6 +389,7 @@ struct vega10_hwmgr {
|
|||
uint32_t config_telemetry;
|
||||
uint32_t smu_version;
|
||||
uint32_t acg_loop_state;
|
||||
uint32_t mem_channels;
|
||||
};
|
||||
|
||||
#define VEGA10_DPM2_NEAR_TDP_DEC 10
|
||||
|
|
|
|||
|
|
@ -234,6 +234,10 @@ int drm_connector_init(struct drm_device *dev,
|
|||
config->link_status_property,
|
||||
0);
|
||||
|
||||
drm_object_attach_property(&connector->base,
|
||||
config->non_desktop_property,
|
||||
0);
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
|
||||
drm_object_attach_property(&connector->base, config->prop_crtc_id, 0);
|
||||
}
|
||||
|
|
@ -763,6 +767,10 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
|
|||
* value of link-status is "GOOD". If something fails during or after modeset,
|
||||
* the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers
|
||||
* should update this value using drm_mode_connector_set_link_status_property().
|
||||
* non_desktop:
|
||||
* Indicates the output should be ignored for purposes of displaying a
|
||||
* standard desktop environment or console. This is most likely because
|
||||
* the output device is not rectilinear.
|
||||
*
|
||||
* Connectors also have one standardized atomic property:
|
||||
*
|
||||
|
|
@ -811,6 +819,11 @@ int drm_connector_create_standard_properties(struct drm_device *dev)
|
|||
return -ENOMEM;
|
||||
dev->mode_config.link_status_property = prop;
|
||||
|
||||
prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop");
|
||||
if (!prop)
|
||||
return -ENOMEM;
|
||||
dev->mode_config.non_desktop_property = prop;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1194,6 +1207,10 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector,
|
|||
if (edid)
|
||||
size = EDID_LENGTH * (1 + edid->extensions);
|
||||
|
||||
drm_object_property_set_value(&connector->base,
|
||||
dev->mode_config.non_desktop_property,
|
||||
connector->display_info.non_desktop);
|
||||
|
||||
ret = drm_property_replace_global_blob(dev,
|
||||
&connector->edid_blob_ptr,
|
||||
size,
|
||||
|
|
|
|||
|
|
@ -82,6 +82,8 @@
|
|||
#define EDID_QUIRK_FORCE_6BPC (1 << 10)
|
||||
/* Force 10bpc */
|
||||
#define EDID_QUIRK_FORCE_10BPC (1 << 11)
|
||||
/* Non desktop display (i.e. HMD) */
|
||||
#define EDID_QUIRK_NON_DESKTOP (1 << 12)
|
||||
|
||||
struct detailed_mode_closure {
|
||||
struct drm_connector *connector;
|
||||
|
|
@ -157,6 +159,9 @@ static const struct edid_quirk {
|
|||
|
||||
/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
|
||||
{ "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
|
||||
|
||||
/* HTC Vive VR Headset */
|
||||
{ "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -4393,7 +4398,7 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
|
|||
}
|
||||
|
||||
static void drm_add_display_info(struct drm_connector *connector,
|
||||
struct edid *edid)
|
||||
struct edid *edid, u32 quirks)
|
||||
{
|
||||
struct drm_display_info *info = &connector->display_info;
|
||||
|
||||
|
|
@ -4407,6 +4412,8 @@ static void drm_add_display_info(struct drm_connector *connector,
|
|||
info->max_tmds_clock = 0;
|
||||
info->dvi_dual = false;
|
||||
|
||||
info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
|
||||
|
||||
if (edid->revision < 3)
|
||||
return;
|
||||
|
||||
|
|
@ -4627,7 +4634,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
|
|||
* To avoid multiple parsing of same block, lets parse that map
|
||||
* from sink info, before parsing CEA modes.
|
||||
*/
|
||||
drm_add_display_info(connector, edid);
|
||||
drm_add_display_info(connector, edid, quirks);
|
||||
|
||||
/*
|
||||
* EDID spec says modes should be preferred in this order:
|
||||
|
|
|
|||
|
|
@ -2033,6 +2033,9 @@ static bool drm_connector_enabled(struct drm_connector *connector, bool strict)
|
|||
{
|
||||
bool enable;
|
||||
|
||||
if (connector->display_info.non_desktop)
|
||||
return false;
|
||||
|
||||
if (strict)
|
||||
enable = connector->status == connector_status_connected;
|
||||
else
|
||||
|
|
@ -2052,7 +2055,8 @@ static void drm_enable_connectors(struct drm_fb_helper *fb_helper,
|
|||
connector = fb_helper->connector_info[i]->connector;
|
||||
enabled[i] = drm_connector_enabled(connector, true);
|
||||
DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
|
||||
enabled[i] ? "yes" : "no");
|
||||
connector->display_info.non_desktop ? "non desktop" : enabled[i] ? "yes" : "no");
|
||||
|
||||
any_enabled |= enabled[i];
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -210,7 +210,6 @@ static int fsl_dcu_drm_pm_suspend(struct device *dev)
|
|||
return PTR_ERR(fsl_dev->state);
|
||||
}
|
||||
|
||||
clk_disable_unprepare(fsl_dev->pix_clk);
|
||||
clk_disable_unprepare(fsl_dev->clk);
|
||||
|
||||
return 0;
|
||||
|
|
@ -233,6 +232,7 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
|
|||
if (fsl_dev->tcon)
|
||||
fsl_tcon_bypass_enable(fsl_dev->tcon);
|
||||
fsl_dcu_drm_init_planes(fsl_dev->drm);
|
||||
enable_irq(fsl_dev->irq);
|
||||
drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
|
||||
|
||||
console_lock();
|
||||
|
|
@ -240,7 +240,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
|
|||
console_unlock();
|
||||
|
||||
drm_kms_helper_poll_enable(fsl_dev->drm);
|
||||
enable_irq(fsl_dev->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -102,7 +102,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
|
|||
{
|
||||
struct drm_encoder *encoder = &fsl_dev->encoder;
|
||||
struct drm_connector *connector = &fsl_dev->connector.base;
|
||||
struct drm_mode_config *mode_config = &fsl_dev->drm->mode_config;
|
||||
int ret;
|
||||
|
||||
fsl_dev->connector.encoder = encoder;
|
||||
|
|
@ -122,10 +121,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
|
|||
if (ret < 0)
|
||||
goto err_sysfs;
|
||||
|
||||
drm_object_property_set_value(&connector->base,
|
||||
mode_config->dpms_property,
|
||||
DRM_MODE_DPMS_OFF);
|
||||
|
||||
ret = drm_panel_attach(panel, connector);
|
||||
if (ret) {
|
||||
dev_err(fsl_dev->dev, "failed to attach panel\n");
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ static void imx_drm_crtc_reset(struct drm_crtc *crtc)
|
|||
|
||||
if (crtc->state) {
|
||||
if (crtc->state->mode_blob)
|
||||
drm_property_unreference_blob(crtc->state->mode_blob);
|
||||
drm_property_blob_put(crtc->state->mode_blob);
|
||||
|
||||
state = to_imx_crtc_state(crtc->state);
|
||||
memset(state, 0, sizeof(*state));
|
||||
|
|
|
|||
|
|
@ -183,7 +183,7 @@ static int imx_pd_register(struct drm_device *drm,
|
|||
&imx_pd_connector_helper_funcs);
|
||||
drm_connector_init(drm, &imxpd->connector,
|
||||
&imx_pd_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_VGA);
|
||||
DRM_MODE_CONNECTOR_DPI);
|
||||
}
|
||||
|
||||
if (imxpd->panel)
|
||||
|
|
|
|||
|
|
@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
|
|||
}
|
||||
|
||||
info->par = rfbdev;
|
||||
info->skip_vt_switch = true;
|
||||
|
||||
ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
|
||||
if (ret) {
|
||||
|
|
|
|||
|
|
@ -174,9 +174,9 @@ struct tegra_sor {
|
|||
|
||||
struct reset_control *rst;
|
||||
struct clk *clk_parent;
|
||||
struct clk *clk_brick;
|
||||
struct clk *clk_safe;
|
||||
struct clk *clk_src;
|
||||
struct clk *clk_out;
|
||||
struct clk *clk_pad;
|
||||
struct clk *clk_dp;
|
||||
struct clk *clk;
|
||||
|
||||
|
|
@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
|
|||
|
||||
clk_disable_unprepare(sor->clk);
|
||||
|
||||
err = clk_set_parent(sor->clk, parent);
|
||||
err = clk_set_parent(sor->clk_out, parent);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -266,24 +266,24 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct tegra_clk_sor_brick {
|
||||
struct tegra_clk_sor_pad {
|
||||
struct clk_hw hw;
|
||||
struct tegra_sor *sor;
|
||||
};
|
||||
|
||||
static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw)
|
||||
static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct tegra_clk_sor_brick, hw);
|
||||
return container_of(hw, struct tegra_clk_sor_pad, hw);
|
||||
}
|
||||
|
||||
static const char * const tegra_clk_sor_brick_parents[] = {
|
||||
static const char * const tegra_clk_sor_pad_parents[] = {
|
||||
"pll_d2_out0", "pll_dp"
|
||||
};
|
||||
|
||||
static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
|
||||
static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct tegra_clk_sor_brick *brick = to_brick(hw);
|
||||
struct tegra_sor *sor = brick->sor;
|
||||
struct tegra_clk_sor_pad *pad = to_pad(hw);
|
||||
struct tegra_sor *sor = pad->sor;
|
||||
u32 value;
|
||||
|
||||
value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
|
||||
|
|
@ -304,10 +304,10 @@ static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
|
||||
static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_clk_sor_brick *brick = to_brick(hw);
|
||||
struct tegra_sor *sor = brick->sor;
|
||||
struct tegra_clk_sor_pad *pad = to_pad(hw);
|
||||
struct tegra_sor *sor = pad->sor;
|
||||
u8 parent = U8_MAX;
|
||||
u32 value;
|
||||
|
||||
|
|
@ -328,33 +328,33 @@ static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
|
|||
return parent;
|
||||
}
|
||||
|
||||
static const struct clk_ops tegra_clk_sor_brick_ops = {
|
||||
.set_parent = tegra_clk_sor_brick_set_parent,
|
||||
.get_parent = tegra_clk_sor_brick_get_parent,
|
||||
static const struct clk_ops tegra_clk_sor_pad_ops = {
|
||||
.set_parent = tegra_clk_sor_pad_set_parent,
|
||||
.get_parent = tegra_clk_sor_pad_get_parent,
|
||||
};
|
||||
|
||||
static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor,
|
||||
const char *name)
|
||||
static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
|
||||
const char *name)
|
||||
{
|
||||
struct tegra_clk_sor_brick *brick;
|
||||
struct tegra_clk_sor_pad *pad;
|
||||
struct clk_init_data init;
|
||||
struct clk *clk;
|
||||
|
||||
brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL);
|
||||
if (!brick)
|
||||
pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
|
||||
if (!pad)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
brick->sor = sor;
|
||||
pad->sor = sor;
|
||||
|
||||
init.name = name;
|
||||
init.flags = 0;
|
||||
init.parent_names = tegra_clk_sor_brick_parents;
|
||||
init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents);
|
||||
init.ops = &tegra_clk_sor_brick_ops;
|
||||
init.parent_names = tegra_clk_sor_pad_parents;
|
||||
init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
|
||||
init.ops = &tegra_clk_sor_pad_ops;
|
||||
|
||||
brick->hw.init = &init;
|
||||
pad->hw.init = &init;
|
||||
|
||||
clk = devm_clk_register(sor->dev, &brick->hw);
|
||||
clk = devm_clk_register(sor->dev, &pad->hw);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -998,8 +998,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
|
|||
|
||||
/* switch to safe parent clock */
|
||||
err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
|
||||
if (err < 0)
|
||||
if (err < 0) {
|
||||
dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
|
||||
value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
|
||||
|
|
@ -2007,8 +2009,10 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
|
|||
|
||||
/* switch to safe parent clock */
|
||||
err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
|
||||
if (err < 0)
|
||||
if (err < 0) {
|
||||
dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
div = clk_get_rate(sor->clk) / 1000000 * 4;
|
||||
|
||||
|
|
@ -2111,13 +2115,17 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
|
|||
tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
|
||||
|
||||
/* switch to parent clock */
|
||||
err = clk_set_parent(sor->clk_src, sor->clk_parent);
|
||||
if (err < 0)
|
||||
dev_err(sor->dev, "failed to set source clock: %d\n", err);
|
||||
|
||||
err = tegra_sor_set_parent_clock(sor, sor->clk_src);
|
||||
if (err < 0)
|
||||
err = clk_set_parent(sor->clk, sor->clk_parent);
|
||||
if (err < 0) {
|
||||
dev_err(sor->dev, "failed to set parent clock: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
|
||||
if (err < 0) {
|
||||
dev_err(sor->dev, "failed to set pad clock: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
|
||||
|
||||
|
|
@ -2628,11 +2636,24 @@ static int tegra_sor_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
|
||||
sor->clk_src = devm_clk_get(&pdev->dev, "source");
|
||||
if (IS_ERR(sor->clk_src)) {
|
||||
err = PTR_ERR(sor->clk_src);
|
||||
dev_err(sor->dev, "failed to get source clock: %d\n",
|
||||
err);
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const char *name;
|
||||
|
||||
/*
|
||||
* For backwards compatibility with Tegra210 device trees,
|
||||
* fall back to the old clock name "source" if the new "out"
|
||||
* clock is not available.
|
||||
*/
|
||||
if (of_property_match_string(np, "clock-names", "out") < 0)
|
||||
name = "source";
|
||||
else
|
||||
name = "out";
|
||||
|
||||
sor->clk_out = devm_clk_get(&pdev->dev, name);
|
||||
if (IS_ERR(sor->clk_out)) {
|
||||
err = PTR_ERR(sor->clk_out);
|
||||
dev_err(sor->dev, "failed to get %s clock: %d\n",
|
||||
name, err);
|
||||
goto remove;
|
||||
}
|
||||
}
|
||||
|
|
@ -2658,16 +2679,60 @@ static int tegra_sor_probe(struct platform_device *pdev)
|
|||
goto remove;
|
||||
}
|
||||
|
||||
/*
|
||||
* Starting with Tegra186, the BPMP provides an implementation for
|
||||
* the pad output clock, so we have to look it up from device tree.
|
||||
*/
|
||||
sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
|
||||
if (IS_ERR(sor->clk_pad)) {
|
||||
if (sor->clk_pad != ERR_PTR(-ENOENT)) {
|
||||
err = PTR_ERR(sor->clk_pad);
|
||||
goto remove;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the pad output clock is not available, then we assume
|
||||
* we're on Tegra210 or earlier and have to provide our own
|
||||
* implementation.
|
||||
*/
|
||||
sor->clk_pad = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* The bootloader may have set up the SOR such that it's module clock
|
||||
* is sourced by one of the display PLLs. However, that doesn't work
|
||||
* without properly having set up other bits of the SOR.
|
||||
*/
|
||||
err = clk_set_parent(sor->clk_out, sor->clk_safe);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
|
||||
goto remove;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, sor);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick");
|
||||
pm_runtime_put(&pdev->dev);
|
||||
/*
|
||||
* On Tegra210 and earlier, provide our own implementation for the
|
||||
* pad output clock.
|
||||
*/
|
||||
if (!sor->clk_pad) {
|
||||
err = pm_runtime_get_sync(&pdev->dev);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
|
||||
err);
|
||||
goto remove;
|
||||
}
|
||||
|
||||
if (IS_ERR(sor->clk_brick)) {
|
||||
err = PTR_ERR(sor->clk_brick);
|
||||
dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err);
|
||||
sor->clk_pad = tegra_clk_sor_pad_register(sor,
|
||||
"sor1_pad_clkout");
|
||||
pm_runtime_put(&pdev->dev);
|
||||
}
|
||||
|
||||
if (IS_ERR(sor->clk_pad)) {
|
||||
err = PTR_ERR(sor->clk_pad);
|
||||
dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
|
||||
err);
|
||||
goto remove;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,14 +12,3 @@ config DRM_TILCDC
|
|||
controller, for example AM33xx in beagle-bone, DA8xx, or
|
||||
OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver.
|
||||
|
||||
config DRM_TILCDC_SLAVE_COMPAT
|
||||
bool "Support device tree blobs using TI LCDC Slave binding"
|
||||
depends on DRM_TILCDC
|
||||
default y
|
||||
select OF_RESOLVE
|
||||
select OF_OVERLAY
|
||||
help
|
||||
Choose this option if you need a kernel that is compatible
|
||||
with device tree blobs using the obsolete "ti,tilcdc,slave"
|
||||
binding. If you find "ti,tilcdc,slave"-string from your DTB,
|
||||
you probably need this. Otherwise you do not.
|
||||
|
|
|
|||
|
|
@ -3,9 +3,6 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS)))
|
|||
ccflags-y += -Werror
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \
|
||||
tilcdc_slave_compat.dtb.o
|
||||
|
||||
tilcdc-y := \
|
||||
tilcdc_plane.o \
|
||||
tilcdc_crtc.o \
|
||||
|
|
|
|||
|
|
@ -1,264 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments
|
||||
* Author: Jyri Sarha <jsarha@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* To support the old "ti,tilcdc,slave" binding the binding has to be
|
||||
* transformed to the new external encoder binding.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_graph.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include "tilcdc_slave_compat.h"
|
||||
|
||||
struct kfree_table {
|
||||
int total;
|
||||
int num;
|
||||
void **table;
|
||||
};
|
||||
|
||||
static int __init kfree_table_init(struct kfree_table *kft)
|
||||
{
|
||||
kft->total = 32;
|
||||
kft->num = 0;
|
||||
kft->table = kmalloc(kft->total * sizeof(*kft->table),
|
||||
GFP_KERNEL);
|
||||
if (!kft->table)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init kfree_table_add(struct kfree_table *kft, void *p)
|
||||
{
|
||||
if (kft->num == kft->total) {
|
||||
void **old = kft->table;
|
||||
|
||||
kft->total *= 2;
|
||||
kft->table = krealloc(old, kft->total * sizeof(*kft->table),
|
||||
GFP_KERNEL);
|
||||
if (!kft->table) {
|
||||
kft->table = old;
|
||||
kfree(p);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
kft->table[kft->num++] = p;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init kfree_table_free(struct kfree_table *kft)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < kft->num; i++)
|
||||
kfree(kft->table[i]);
|
||||
|
||||
kfree(kft->table);
|
||||
}
|
||||
|
||||
static
|
||||
struct property * __init tilcdc_prop_dup(const struct property *prop,
|
||||
struct kfree_table *kft)
|
||||
{
|
||||
struct property *nprop;
|
||||
|
||||
nprop = kzalloc(sizeof(*nprop), GFP_KERNEL);
|
||||
if (!nprop || kfree_table_add(kft, nprop))
|
||||
return NULL;
|
||||
|
||||
nprop->name = kstrdup(prop->name, GFP_KERNEL);
|
||||
if (!nprop->name || kfree_table_add(kft, nprop->name))
|
||||
return NULL;
|
||||
|
||||
nprop->value = kmemdup(prop->value, prop->length, GFP_KERNEL);
|
||||
if (!nprop->value || kfree_table_add(kft, nprop->value))
|
||||
return NULL;
|
||||
|
||||
nprop->length = prop->length;
|
||||
|
||||
return nprop;
|
||||
}
|
||||
|
||||
static void __init tilcdc_copy_props(struct device_node *from,
|
||||
struct device_node *to,
|
||||
const char * const props[],
|
||||
struct kfree_table *kft)
|
||||
{
|
||||
struct property *prop;
|
||||
int i;
|
||||
|
||||
for (i = 0; props[i]; i++) {
|
||||
prop = of_find_property(from, props[i], NULL);
|
||||
if (!prop)
|
||||
continue;
|
||||
|
||||
prop = tilcdc_prop_dup(prop, kft);
|
||||
if (!prop)
|
||||
continue;
|
||||
|
||||
prop->next = to->properties;
|
||||
to->properties = prop;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init tilcdc_prop_str_update(struct property *prop,
|
||||
const char *str,
|
||||
struct kfree_table *kft)
|
||||
{
|
||||
prop->value = kstrdup(str, GFP_KERNEL);
|
||||
if (kfree_table_add(kft, prop->value) || !prop->value)
|
||||
return -ENOMEM;
|
||||
prop->length = strlen(str)+1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init tilcdc_node_disable(struct device_node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
|
||||
prop = kzalloc(sizeof(*prop), GFP_KERNEL);
|
||||
if (!prop)
|
||||
return;
|
||||
|
||||
prop->name = "status";
|
||||
prop->value = "disabled";
|
||||
prop->length = strlen((char *)prop->value)+1;
|
||||
|
||||
of_update_property(node, prop);
|
||||
}
|
||||
|
||||
static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
|
||||
{
|
||||
const int size = __dtb_tilcdc_slave_compat_end -
|
||||
__dtb_tilcdc_slave_compat_begin;
|
||||
static void *overlay_data;
|
||||
struct device_node *overlay;
|
||||
|
||||
if (!size) {
|
||||
pr_warn("%s: No overlay data\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
overlay_data = kmemdup(__dtb_tilcdc_slave_compat_begin,
|
||||
size, GFP_KERNEL);
|
||||
if (!overlay_data || kfree_table_add(kft, overlay_data))
|
||||
return NULL;
|
||||
|
||||
of_fdt_unflatten_tree(overlay_data, NULL, &overlay);
|
||||
if (!overlay) {
|
||||
pr_warn("%s: Unfattening overlay tree failed\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return overlay;
|
||||
}
|
||||
|
||||
static const struct of_device_id tilcdc_slave_of_match[] __initconst = {
|
||||
{ .compatible = "ti,tilcdc,slave", },
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct of_device_id tilcdc_of_match[] __initconst = {
|
||||
{ .compatible = "ti,am33xx-tilcdc", },
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct of_device_id tilcdc_tda998x_of_match[] __initconst = {
|
||||
{ .compatible = "nxp,tda998x", },
|
||||
{},
|
||||
};
|
||||
|
||||
static const char * const tilcdc_slave_props[] __initconst = {
|
||||
"pinctrl-names",
|
||||
"pinctrl-0",
|
||||
"pinctrl-1",
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init tilcdc_convert_slave_node(void)
|
||||
{
|
||||
struct device_node *slave = NULL, *lcdc = NULL;
|
||||
struct device_node *i2c = NULL, *fragment = NULL;
|
||||
struct device_node *overlay, *encoder;
|
||||
struct property *prop;
|
||||
/* For all memory needed for the overlay tree. This memory can
|
||||
be freed after the overlay has been applied. */
|
||||
struct kfree_table kft;
|
||||
int ovcs_id, ret;
|
||||
|
||||
if (kfree_table_init(&kft))
|
||||
return;
|
||||
|
||||
lcdc = of_find_matching_node(NULL, tilcdc_of_match);
|
||||
slave = of_find_matching_node(NULL, tilcdc_slave_of_match);
|
||||
|
||||
if (!slave || !of_device_is_available(lcdc))
|
||||
goto out;
|
||||
|
||||
i2c = of_parse_phandle(slave, "i2c", 0);
|
||||
if (!i2c) {
|
||||
pr_err("%s: Can't find i2c node trough phandle\n", __func__);
|
||||
goto out;
|
||||
}
|
||||
|
||||
overlay = tilcdc_get_overlay(&kft);
|
||||
if (!overlay)
|
||||
goto out;
|
||||
|
||||
encoder = of_find_matching_node(overlay, tilcdc_tda998x_of_match);
|
||||
if (!encoder) {
|
||||
pr_err("%s: Failed to find tda998x node\n", __func__);
|
||||
goto out;
|
||||
}
|
||||
|
||||
tilcdc_copy_props(slave, encoder, tilcdc_slave_props, &kft);
|
||||
|
||||
for_each_child_of_node(overlay, fragment) {
|
||||
prop = of_find_property(fragment, "target-path", NULL);
|
||||
if (!prop)
|
||||
continue;
|
||||
if (!strncmp("i2c", (char *)prop->value, prop->length))
|
||||
if (tilcdc_prop_str_update(prop, i2c->full_name, &kft))
|
||||
goto out;
|
||||
if (!strncmp("lcdc", (char *)prop->value, prop->length))
|
||||
if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft))
|
||||
goto out;
|
||||
}
|
||||
|
||||
tilcdc_node_disable(slave);
|
||||
|
||||
ovcs_id = 0;
|
||||
ret = of_overlay_apply(overlay, &ovcs_id);
|
||||
if (ret)
|
||||
pr_err("%s: Applying overlay changeset failed: %d\n",
|
||||
__func__, ret);
|
||||
else
|
||||
pr_info("%s: ti,tilcdc,slave node successfully converted\n",
|
||||
__func__);
|
||||
out:
|
||||
kfree_table_free(&kft);
|
||||
of_node_put(i2c);
|
||||
of_node_put(slave);
|
||||
of_node_put(lcdc);
|
||||
of_node_put(fragment);
|
||||
}
|
||||
|
||||
static int __init tilcdc_slave_compat_init(void)
|
||||
{
|
||||
tilcdc_convert_slave_node();
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(tilcdc_slave_compat_init);
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
/*
|
||||
* DTS overlay for converting ti,tilcdc,slave binding to new binding.
|
||||
*
|
||||
* Copyright (C) 2015 Texas Instruments Inc.
|
||||
* Author: Jyri Sarha <jsarha@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* target-path property values are simple tags that are replaced with
|
||||
* correct values in tildcdc_slave_compat.c. Some properties are also
|
||||
* copied over from the ti,tilcdc,slave node.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
fragment@0 {
|
||||
target-path = "i2c";
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
tda19988 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
hdmi_0: endpoint@0 {
|
||||
remote-endpoint = <&lcd_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "lcdc";
|
||||
__overlay__ {
|
||||
port {
|
||||
lcd_0: endpoint@0 {
|
||||
remote-endpoint = <&hdmi_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__local_fixups__ {
|
||||
fragment@0 {
|
||||
__overlay__ {
|
||||
tda19988 {
|
||||
port {
|
||||
endpoint@0 {
|
||||
remote-endpoint = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
fragment@1 {
|
||||
__overlay__ {
|
||||
port {
|
||||
endpoint@0 {
|
||||
remote-endpoint = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments
|
||||
* Author: Jyri Sarha <jsarha@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/* This header declares the symbols defined in tilcdc_slave_compat.dts */
|
||||
|
||||
#ifndef __TILCDC_SLAVE_COMPAT_H__
|
||||
#define __TILCDC_SLAVE_COMPAT_H__
|
||||
|
||||
extern uint8_t __dtb_tilcdc_slave_compat_begin[];
|
||||
extern uint8_t __dtb_tilcdc_slave_compat_end[];
|
||||
|
||||
#endif /* __TILCDC_SLAVE_COMPAT_H__ */
|
||||
|
|
@ -249,11 +249,8 @@ EXPORT_SYMBOL_GPL(ipu_dc_enable);
|
|||
|
||||
void ipu_dc_enable_channel(struct ipu_dc *dc)
|
||||
{
|
||||
int di;
|
||||
u32 reg;
|
||||
|
||||
di = dc->di;
|
||||
|
||||
reg = readl(dc->base + DC_WR_CH_CONF);
|
||||
reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
|
||||
writel(reg, dc->base + DC_WR_CH_CONF);
|
||||
|
|
|
|||
|
|
@ -284,6 +284,11 @@ struct drm_display_info {
|
|||
* @hdmi: advance features of a HDMI sink.
|
||||
*/
|
||||
struct drm_hdmi_info hdmi;
|
||||
|
||||
/**
|
||||
* @non_desktop: Non desktop display (HMD).
|
||||
*/
|
||||
bool non_desktop;
|
||||
};
|
||||
|
||||
int drm_display_info_set_bus_formats(struct drm_display_info *info,
|
||||
|
|
|
|||
|
|
@ -728,6 +728,13 @@ struct drm_mode_config {
|
|||
*/
|
||||
struct drm_property *suggested_y_property;
|
||||
|
||||
/**
|
||||
* @non_desktop_property: Optional connector property with a hint
|
||||
* that device isn't a standard display, and the console/desktop,
|
||||
* should not be displayed on it.
|
||||
*/
|
||||
struct drm_property *non_desktop_property;
|
||||
|
||||
/* dumb ioctl parameters */
|
||||
uint32_t preferred_depth, prefer_shadow;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,887 +0,0 @@
|
|||
/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MSM_BUS_IDS_H
|
||||
#define __MSM_BUS_IDS_H
|
||||
|
||||
/* Aggregation types */
|
||||
#define AGG_SCHEME_NONE 0
|
||||
#define AGG_SCHEME_LEG 1
|
||||
#define AGG_SCHEME_1 2
|
||||
|
||||
/* Topology related enums */
|
||||
#define MSM_BUS_FAB_DEFAULT 0
|
||||
#define MSM_BUS_FAB_APPSS 0
|
||||
#define MSM_BUS_FAB_SYSTEM 1024
|
||||
#define MSM_BUS_FAB_MMSS 2048
|
||||
#define MSM_BUS_FAB_SYSTEM_FPB 3072
|
||||
#define MSM_BUS_FAB_CPSS_FPB 4096
|
||||
|
||||
#define MSM_BUS_FAB_BIMC 0
|
||||
#define MSM_BUS_FAB_SYS_NOC 1024
|
||||
#define MSM_BUS_FAB_MMSS_NOC 2048
|
||||
#define MSM_BUS_FAB_OCMEM_NOC 3072
|
||||
#define MSM_BUS_FAB_PERIPH_NOC 4096
|
||||
#define MSM_BUS_FAB_CONFIG_NOC 5120
|
||||
#define MSM_BUS_FAB_OCMEM_VNOC 6144
|
||||
#define MSM_BUS_FAB_MMSS_AHB 2049
|
||||
#define MSM_BUS_FAB_A0_NOC 6145
|
||||
#define MSM_BUS_FAB_A1_NOC 6146
|
||||
#define MSM_BUS_FAB_A2_NOC 6147
|
||||
#define MSM_BUS_FAB_GNOC 6148
|
||||
#define MSM_BUS_FAB_CR_VIRT 6149
|
||||
|
||||
#define MSM_BUS_MASTER_FIRST 1
|
||||
#define MSM_BUS_MASTER_AMPSS_M0 1
|
||||
#define MSM_BUS_MASTER_AMPSS_M1 2
|
||||
#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3
|
||||
#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
|
||||
#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
|
||||
#define MSM_BUS_MASTER_SPS 6
|
||||
#define MSM_BUS_MASTER_ADM_PORT0 7
|
||||
#define MSM_BUS_MASTER_ADM_PORT1 8
|
||||
#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
|
||||
#define MSM_BUS_MASTER_ADM1_PORT1 10
|
||||
#define MSM_BUS_MASTER_LPASS_PROC 11
|
||||
#define MSM_BUS_MASTER_MSS_PROCI 12
|
||||
#define MSM_BUS_MASTER_MSS_PROCD 13
|
||||
#define MSM_BUS_MASTER_MSS_MDM_PORT0 14
|
||||
#define MSM_BUS_MASTER_LPASS 15
|
||||
#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
|
||||
#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
|
||||
#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
|
||||
#define MSM_BUS_MASTER_ADM1_CI 19
|
||||
#define MSM_BUS_MASTER_ADM0_CI 20
|
||||
#define MSM_BUS_MASTER_MSS_MDM_PORT1 21
|
||||
#define MSM_BUS_MASTER_MDP_PORT0 22
|
||||
#define MSM_BUS_MASTER_MDP_PORT1 23
|
||||
#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
|
||||
#define MSM_BUS_MASTER_ROTATOR 25
|
||||
#define MSM_BUS_MASTER_GRAPHICS_3D 26
|
||||
#define MSM_BUS_MASTER_JPEG_DEC 27
|
||||
#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
|
||||
#define MSM_BUS_MASTER_VFE 29
|
||||
#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE
|
||||
#define MSM_BUS_MASTER_VPE 30
|
||||
#define MSM_BUS_MASTER_JPEG_ENC 31
|
||||
#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
|
||||
#define MSM_BUS_MMSS_MASTER_APPS_FAB 33
|
||||
#define MSM_BUS_MASTER_HD_CODEC_PORT0 34
|
||||
#define MSM_BUS_MASTER_HD_CODEC_PORT1 35
|
||||
#define MSM_BUS_MASTER_SPDM 36
|
||||
#define MSM_BUS_MASTER_RPM 37
|
||||
#define MSM_BUS_MASTER_MSS 38
|
||||
#define MSM_BUS_MASTER_RIVA 39
|
||||
#define MSM_BUS_MASTER_SNOC_VMEM 40
|
||||
#define MSM_BUS_MASTER_MSS_SW_PROC 41
|
||||
#define MSM_BUS_MASTER_MSS_FW_PROC 42
|
||||
#define MSM_BUS_MASTER_HMSS 43
|
||||
#define MSM_BUS_MASTER_GSS_NAV 44
|
||||
#define MSM_BUS_MASTER_PCIE 45
|
||||
#define MSM_BUS_MASTER_SATA 46
|
||||
#define MSM_BUS_MASTER_CRYPTO 47
|
||||
#define MSM_BUS_MASTER_VIDEO_CAP 48
|
||||
#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
|
||||
#define MSM_BUS_MASTER_VIDEO_ENC 50
|
||||
#define MSM_BUS_MASTER_VIDEO_DEC 51
|
||||
#define MSM_BUS_MASTER_LPASS_AHB 52
|
||||
#define MSM_BUS_MASTER_QDSS_BAM 53
|
||||
#define MSM_BUS_MASTER_SNOC_CFG 54
|
||||
#define MSM_BUS_MASTER_CRYPTO_CORE0 55
|
||||
#define MSM_BUS_MASTER_CRYPTO_CORE1 56
|
||||
#define MSM_BUS_MASTER_MSS_NAV 57
|
||||
#define MSM_BUS_MASTER_OCMEM_DMA 58
|
||||
#define MSM_BUS_MASTER_WCSS 59
|
||||
#define MSM_BUS_MASTER_QDSS_ETR 60
|
||||
#define MSM_BUS_MASTER_USB3 61
|
||||
#define MSM_BUS_MASTER_JPEG 62
|
||||
#define MSM_BUS_MASTER_VIDEO_P0 63
|
||||
#define MSM_BUS_MASTER_VIDEO_P1 64
|
||||
#define MSM_BUS_MASTER_MSS_PROC 65
|
||||
#define MSM_BUS_MASTER_JPEG_OCMEM 66
|
||||
#define MSM_BUS_MASTER_MDP_OCMEM 67
|
||||
#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
|
||||
#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
|
||||
#define MSM_BUS_MASTER_VFE_OCMEM 70
|
||||
#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71
|
||||
#define MSM_BUS_MASTER_RPM_INST 72
|
||||
#define MSM_BUS_MASTER_RPM_DATA 73
|
||||
#define MSM_BUS_MASTER_RPM_SYS 74
|
||||
#define MSM_BUS_MASTER_DEHR 75
|
||||
#define MSM_BUS_MASTER_QDSS_DAP 76
|
||||
#define MSM_BUS_MASTER_TIC 77
|
||||
#define MSM_BUS_MASTER_SDCC_1 78
|
||||
#define MSM_BUS_MASTER_SDCC_3 79
|
||||
#define MSM_BUS_MASTER_SDCC_4 80
|
||||
#define MSM_BUS_MASTER_SDCC_2 81
|
||||
#define MSM_BUS_MASTER_TSIF 82
|
||||
#define MSM_BUS_MASTER_BAM_DMA 83
|
||||
#define MSM_BUS_MASTER_BLSP_2 84
|
||||
#define MSM_BUS_MASTER_USB_HSIC 85
|
||||
#define MSM_BUS_MASTER_BLSP_1 86
|
||||
#define MSM_BUS_MASTER_USB_HS 87
|
||||
#define MSM_BUS_MASTER_PNOC_CFG 88
|
||||
#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89
|
||||
#define MSM_BUS_MASTER_IPA 90
|
||||
#define MSM_BUS_MASTER_QPIC 91
|
||||
#define MSM_BUS_MASTER_MDPE 92
|
||||
#define MSM_BUS_MASTER_USB_HS2 93
|
||||
#define MSM_BUS_MASTER_VPU 94
|
||||
#define MSM_BUS_MASTER_UFS 95
|
||||
#define MSM_BUS_MASTER_BCAST 96
|
||||
#define MSM_BUS_MASTER_CRYPTO_CORE2 97
|
||||
#define MSM_BUS_MASTER_EMAC 98
|
||||
#define MSM_BUS_MASTER_VPU_1 99
|
||||
#define MSM_BUS_MASTER_PCIE_1 100
|
||||
#define MSM_BUS_MASTER_USB3_1 101
|
||||
#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
|
||||
#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103
|
||||
#define MSM_BUS_MASTER_TCU_0 104
|
||||
#define MSM_BUS_MASTER_TCU_1 105
|
||||
#define MSM_BUS_MASTER_CPP 106
|
||||
#define MSM_BUS_MASTER_AUDIO 107
|
||||
#define MSM_BUS_MASTER_PCIE_2 108
|
||||
#define MSM_BUS_MASTER_VFE1 109
|
||||
#define MSM_BUS_MASTER_XM_USB_HS1 110
|
||||
#define MSM_BUS_MASTER_PCNOC_BIMC_1 111
|
||||
#define MSM_BUS_MASTER_BIMC_PCNOC 112
|
||||
#define MSM_BUS_MASTER_XI_USB_HSIC 113
|
||||
#define MSM_BUS_MASTER_SGMII 114
|
||||
#define MSM_BUS_SPMI_FETCHER 115
|
||||
#define MSM_BUS_MASTER_GNOC_BIMC 116
|
||||
#define MSM_BUS_MASTER_CRVIRT_A2NOC 117
|
||||
#define MSM_BUS_MASTER_CNOC_A2NOC 118
|
||||
#define MSM_BUS_MASTER_WLAN 119
|
||||
#define MSM_BUS_MASTER_MSS_CE 120
|
||||
#define MSM_BUS_MASTER_CDSP_PROC 121
|
||||
#define MSM_BUS_MASTER_GNOC_SNOC 122
|
||||
#define MSM_BUS_MASTER_PIMEM 123
|
||||
#define MSM_BUS_MASTER_MASTER_LAST 124
|
||||
|
||||
#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
|
||||
#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
|
||||
|
||||
#define MSM_BUS_SNOC_MM_INT_0 10000
|
||||
#define MSM_BUS_SNOC_MM_INT_1 10001
|
||||
#define MSM_BUS_SNOC_MM_INT_2 10002
|
||||
#define MSM_BUS_SNOC_MM_INT_BIMC 10003
|
||||
#define MSM_BUS_SNOC_INT_0 10004
|
||||
#define MSM_BUS_SNOC_INT_1 10005
|
||||
#define MSM_BUS_SNOC_INT_BIMC 10006
|
||||
#define MSM_BUS_SNOC_BIMC_0_MAS 10007
|
||||
#define MSM_BUS_SNOC_BIMC_1_MAS 10008
|
||||
#define MSM_BUS_SNOC_QDSS_INT 10009
|
||||
#define MSM_BUS_PNOC_SNOC_MAS 10010
|
||||
#define MSM_BUS_PNOC_SNOC_SLV 10011
|
||||
#define MSM_BUS_PNOC_INT_0 10012
|
||||
#define MSM_BUS_PNOC_INT_1 10013
|
||||
#define MSM_BUS_PNOC_M_0 10014
|
||||
#define MSM_BUS_PNOC_M_1 10015
|
||||
#define MSM_BUS_BIMC_SNOC_MAS 10016
|
||||
#define MSM_BUS_BIMC_SNOC_SLV 10017
|
||||
#define MSM_BUS_PNOC_SLV_0 10018
|
||||
#define MSM_BUS_PNOC_SLV_1 10019
|
||||
#define MSM_BUS_PNOC_SLV_2 10020
|
||||
#define MSM_BUS_PNOC_SLV_3 10021
|
||||
#define MSM_BUS_PNOC_SLV_4 10022
|
||||
#define MSM_BUS_PNOC_SLV_8 10023
|
||||
#define MSM_BUS_PNOC_SLV_9 10024
|
||||
#define MSM_BUS_SNOC_BIMC_0_SLV 10025
|
||||
#define MSM_BUS_SNOC_BIMC_1_SLV 10026
|
||||
#define MSM_BUS_MNOC_BIMC_MAS 10027
|
||||
#define MSM_BUS_MNOC_BIMC_SLV 10028
|
||||
#define MSM_BUS_BIMC_MNOC_MAS 10029
|
||||
#define MSM_BUS_BIMC_MNOC_SLV 10030
|
||||
#define MSM_BUS_SNOC_BIMC_MAS 10031
|
||||
#define MSM_BUS_SNOC_BIMC_SLV 10032
|
||||
#define MSM_BUS_CNOC_SNOC_MAS 10033
|
||||
#define MSM_BUS_CNOC_SNOC_SLV 10034
|
||||
#define MSM_BUS_SNOC_CNOC_MAS 10035
|
||||
#define MSM_BUS_SNOC_CNOC_SLV 10036
|
||||
#define MSM_BUS_OVNOC_SNOC_MAS 10037
|
||||
#define MSM_BUS_OVNOC_SNOC_SLV 10038
|
||||
#define MSM_BUS_SNOC_OVNOC_MAS 10039
|
||||
#define MSM_BUS_SNOC_OVNOC_SLV 10040
|
||||
#define MSM_BUS_SNOC_PNOC_MAS 10041
|
||||
#define MSM_BUS_SNOC_PNOC_SLV 10042
|
||||
#define MSM_BUS_BIMC_INT_APPS_EBI 10043
|
||||
#define MSM_BUS_BIMC_INT_APPS_SNOC 10044
|
||||
#define MSM_BUS_SNOC_BIMC_2_MAS 10045
|
||||
#define MSM_BUS_SNOC_BIMC_2_SLV 10046
|
||||
#define MSM_BUS_PNOC_SLV_5 10047
|
||||
#define MSM_BUS_PNOC_SLV_7 10048
|
||||
#define MSM_BUS_PNOC_INT_2 10049
|
||||
#define MSM_BUS_PNOC_INT_3 10050
|
||||
#define MSM_BUS_PNOC_INT_4 10051
|
||||
#define MSM_BUS_PNOC_INT_5 10052
|
||||
#define MSM_BUS_PNOC_INT_6 10053
|
||||
#define MSM_BUS_PNOC_INT_7 10054
|
||||
#define MSM_BUS_BIMC_SNOC_1_MAS 10055
|
||||
#define MSM_BUS_BIMC_SNOC_1_SLV 10056
|
||||
#define MSM_BUS_PNOC_A1NOC_MAS 10057
|
||||
#define MSM_BUS_PNOC_A1NOC_SLV 10058
|
||||
#define MSM_BUS_CNOC_A1NOC_MAS 10059
|
||||
#define MSM_BUS_A0NOC_SNOC_MAS 10060
|
||||
#define MSM_BUS_A0NOC_SNOC_SLV 10061
|
||||
#define MSM_BUS_A1NOC_SNOC_SLV 10062
|
||||
#define MSM_BUS_A1NOC_SNOC_MAS 10063
|
||||
#define MSM_BUS_A2NOC_SNOC_MAS 10064
|
||||
#define MSM_BUS_A2NOC_SNOC_SLV 10065
|
||||
#define MSM_BUS_SNOC_INT_2 10066
|
||||
#define MSM_BUS_A0NOC_QDSS_INT 10067
|
||||
#define MSM_BUS_INT_LAST 10068
|
||||
|
||||
#define MSM_BUS_INT_TEST_ID 20000
|
||||
#define MSM_BUS_INT_TEST_LAST 20050
|
||||
|
||||
#define MSM_BUS_SLAVE_FIRST 512
|
||||
#define MSM_BUS_SLAVE_EBI_CH0 512
|
||||
#define MSM_BUS_SLAVE_EBI_CH1 513
|
||||
#define MSM_BUS_SLAVE_AMPSS_L2 514
|
||||
#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
|
||||
#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
|
||||
#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
|
||||
#define MSM_BUS_SLAVE_SPS 518
|
||||
#define MSM_BUS_SLAVE_SYSTEM_IMEM 519
|
||||
#define MSM_BUS_SLAVE_AMPSS 520
|
||||
#define MSM_BUS_SLAVE_MSS 521
|
||||
#define MSM_BUS_SLAVE_LPASS 522
|
||||
#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
|
||||
#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
|
||||
#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
|
||||
#define MSM_BUS_SLAVE_CORESIGHT 526
|
||||
#define MSM_BUS_SLAVE_RIVA 527
|
||||
#define MSM_BUS_SLAVE_SMI 528
|
||||
#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529
|
||||
#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
|
||||
#define MSM_BUS_SLAVE_MM_IMEM 531
|
||||
#define MSM_BUS_SLAVE_CRYPTO 532
|
||||
#define MSM_BUS_SLAVE_SPDM 533
|
||||
#define MSM_BUS_SLAVE_RPM 534
|
||||
#define MSM_BUS_SLAVE_RPM_MSG_RAM 535
|
||||
#define MSM_BUS_SLAVE_MPM 536
|
||||
#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
|
||||
#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
|
||||
#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
|
||||
#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
|
||||
#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
|
||||
#define MSM_BUS_SLAVE_GSBI1_UART 542
|
||||
#define MSM_BUS_SLAVE_GSBI2_UART 543
|
||||
#define MSM_BUS_SLAVE_GSBI3_UART 544
|
||||
#define MSM_BUS_SLAVE_GSBI4_UART 545
|
||||
#define MSM_BUS_SLAVE_GSBI5_UART 546
|
||||
#define MSM_BUS_SLAVE_GSBI6_UART 547
|
||||
#define MSM_BUS_SLAVE_GSBI7_UART 548
|
||||
#define MSM_BUS_SLAVE_GSBI8_UART 549
|
||||
#define MSM_BUS_SLAVE_GSBI9_UART 550
|
||||
#define MSM_BUS_SLAVE_GSBI10_UART 551
|
||||
#define MSM_BUS_SLAVE_GSBI11_UART 552
|
||||
#define MSM_BUS_SLAVE_GSBI12_UART 553
|
||||
#define MSM_BUS_SLAVE_GSBI1_QUP 554
|
||||
#define MSM_BUS_SLAVE_GSBI2_QUP 555
|
||||
#define MSM_BUS_SLAVE_GSBI3_QUP 556
|
||||
#define MSM_BUS_SLAVE_GSBI4_QUP 557
|
||||
#define MSM_BUS_SLAVE_GSBI5_QUP 558
|
||||
#define MSM_BUS_SLAVE_GSBI6_QUP 559
|
||||
#define MSM_BUS_SLAVE_GSBI7_QUP 560
|
||||
#define MSM_BUS_SLAVE_GSBI8_QUP 561
|
||||
#define MSM_BUS_SLAVE_GSBI9_QUP 562
|
||||
#define MSM_BUS_SLAVE_GSBI10_QUP 563
|
||||
#define MSM_BUS_SLAVE_GSBI11_QUP 564
|
||||
#define MSM_BUS_SLAVE_GSBI12_QUP 565
|
||||
#define MSM_BUS_SLAVE_EBI2_NAND 566
|
||||
#define MSM_BUS_SLAVE_EBI2_CS0 567
|
||||
#define MSM_BUS_SLAVE_EBI2_CS1 568
|
||||
#define MSM_BUS_SLAVE_EBI2_CS2 569
|
||||
#define MSM_BUS_SLAVE_EBI2_CS3 570
|
||||
#define MSM_BUS_SLAVE_EBI2_CS4 571
|
||||
#define MSM_BUS_SLAVE_EBI2_CS5 572
|
||||
#define MSM_BUS_SLAVE_USB_FS1 573
|
||||
#define MSM_BUS_SLAVE_USB_FS2 574
|
||||
#define MSM_BUS_SLAVE_TSIF 575
|
||||
#define MSM_BUS_SLAVE_MSM_TSSC 576
|
||||
#define MSM_BUS_SLAVE_MSM_PDM 577
|
||||
#define MSM_BUS_SLAVE_MSM_DIMEM 578
|
||||
#define MSM_BUS_SLAVE_MSM_TCSR 579
|
||||
#define MSM_BUS_SLAVE_MSM_PRNG 580
|
||||
#define MSM_BUS_SLAVE_GSS 581
|
||||
#define MSM_BUS_SLAVE_SATA 582
|
||||
#define MSM_BUS_SLAVE_USB3 583
|
||||
#define MSM_BUS_SLAVE_WCSS 584
|
||||
#define MSM_BUS_SLAVE_OCIMEM 585
|
||||
#define MSM_BUS_SLAVE_SNOC_OCMEM 586
|
||||
#define MSM_BUS_SLAVE_SERVICE_SNOC 587
|
||||
#define MSM_BUS_SLAVE_QDSS_STM 588
|
||||
#define MSM_BUS_SLAVE_CAMERA_CFG 589
|
||||
#define MSM_BUS_SLAVE_DISPLAY_CFG 590
|
||||
#define MSM_BUS_SLAVE_OCMEM_CFG 591
|
||||
#define MSM_BUS_SLAVE_CPR_CFG 592
|
||||
#define MSM_BUS_SLAVE_CPR_XPU_CFG 593
|
||||
#define MSM_BUS_SLAVE_MISC_CFG 594
|
||||
#define MSM_BUS_SLAVE_MISC_XPU_CFG 595
|
||||
#define MSM_BUS_SLAVE_VENUS_CFG 596
|
||||
#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597
|
||||
#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
|
||||
#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599
|
||||
#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
|
||||
#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601
|
||||
#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602
|
||||
#define MSM_BUS_SLAVE_SERVICE_MNOC 603
|
||||
#define MSM_BUS_SLAVE_OCMEM 604
|
||||
#define MSM_BUS_SLAVE_SERVICE_ONOC 605
|
||||
#define MSM_BUS_SLAVE_SDCC_1 606
|
||||
#define MSM_BUS_SLAVE_SDCC_3 607
|
||||
#define MSM_BUS_SLAVE_SDCC_2 608
|
||||
#define MSM_BUS_SLAVE_SDCC_4 609
|
||||
#define MSM_BUS_SLAVE_BAM_DMA 610
|
||||
#define MSM_BUS_SLAVE_BLSP_2 611
|
||||
#define MSM_BUS_SLAVE_USB_HSIC 612
|
||||
#define MSM_BUS_SLAVE_BLSP_1 613
|
||||
#define MSM_BUS_SLAVE_USB_HS 614
|
||||
#define MSM_BUS_SLAVE_PDM 615
|
||||
#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616
|
||||
#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617
|
||||
#define MSM_BUS_SLAVE_PRNG 618
|
||||
#define MSM_BUS_SLAVE_SERVICE_PNOC 619
|
||||
#define MSM_BUS_SLAVE_CLK_CTL 620
|
||||
#define MSM_BUS_SLAVE_CNOC_MSS 621
|
||||
#define MSM_BUS_SLAVE_SECURITY 622
|
||||
#define MSM_BUS_SLAVE_TCSR 623
|
||||
#define MSM_BUS_SLAVE_TLMM 624
|
||||
#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625
|
||||
#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626
|
||||
#define MSM_BUS_SLAVE_IMEM_CFG 627
|
||||
#define MSM_BUS_SLAVE_MESSAGE_RAM 628
|
||||
#define MSM_BUS_SLAVE_BIMC_CFG 629
|
||||
#define MSM_BUS_SLAVE_BOOT_ROM 630
|
||||
#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
|
||||
#define MSM_BUS_SLAVE_PMIC_ARB 632
|
||||
#define MSM_BUS_SLAVE_SPDM_WRAPPER 633
|
||||
#define MSM_BUS_SLAVE_DEHR_CFG 634
|
||||
#define MSM_BUS_SLAVE_QDSS_CFG 635
|
||||
#define MSM_BUS_SLAVE_RBCPR_CFG 636
|
||||
#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
|
||||
#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638
|
||||
#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
|
||||
#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
|
||||
#define MSM_BUS_SLAVE_PNOC_CFG 641
|
||||
#define MSM_BUS_SLAVE_SNOC_CFG 642
|
||||
#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643
|
||||
#define MSM_BUS_SLAVE_PHY_APU_CFG 644
|
||||
#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645
|
||||
#define MSM_BUS_SLAVE_SERVICE_CNOC 646
|
||||
#define MSM_BUS_SLAVE_IPS_CFG 647
|
||||
#define MSM_BUS_SLAVE_QPIC 648
|
||||
#define MSM_BUS_SLAVE_DSI_CFG 649
|
||||
#define MSM_BUS_SLAVE_UFS_CFG 650
|
||||
#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651
|
||||
#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652
|
||||
#define MSM_BUS_SLAVE_PCIE_CFG 653
|
||||
#define MSM_BUS_SLAVE_USB_PHYS_CFG 654
|
||||
#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
|
||||
#define MSM_BUS_SLAVE_AVSYNC_CFG 656
|
||||
#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657
|
||||
#define MSM_BUS_SLAVE_VPU_CFG 658
|
||||
#define MSM_BUS_SLAVE_BCAST_CFG 659
|
||||
#define MSM_BUS_SLAVE_KLM_CFG 660
|
||||
#define MSM_BUS_SLAVE_GENI_IR_CFG 661
|
||||
#define MSM_BUS_SLAVE_OCMEM_GFX 662
|
||||
#define MSM_BUS_SLAVE_CATS_128 663
|
||||
#define MSM_BUS_SLAVE_OCMEM_64 664
|
||||
#define MSM_BUS_SLAVE_PCIE_0 665
|
||||
#define MSM_BUS_SLAVE_PCIE_1 666
|
||||
#define MSM_BUS_SLAVE_PCIE_0_CFG 667
|
||||
#define MSM_BUS_SLAVE_PCIE_1_CFG 668
|
||||
#define MSM_BUS_SLAVE_SRVC_MNOC 669
|
||||
#define MSM_BUS_SLAVE_USB_HS2 670
|
||||
#define MSM_BUS_SLAVE_AUDIO 671
|
||||
#define MSM_BUS_SLAVE_TCU 672
|
||||
#define MSM_BUS_SLAVE_APPSS 673
|
||||
#define MSM_BUS_SLAVE_PCIE_PARF 674
|
||||
#define MSM_BUS_SLAVE_USB3_PHY_CFG 675
|
||||
#define MSM_BUS_SLAVE_IPA_CFG 676
|
||||
#define MSM_BUS_SLAVE_A0NOC_SNOC 677
|
||||
#define MSM_BUS_SLAVE_A1NOC_SNOC 678
|
||||
#define MSM_BUS_SLAVE_A2NOC_SNOC 679
|
||||
#define MSM_BUS_SLAVE_HMSS_L3 680
|
||||
#define MSM_BUS_SLAVE_PIMEM_CFG 681
|
||||
#define MSM_BUS_SLAVE_DCC_CFG 682
|
||||
#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
|
||||
#define MSM_BUS_SLAVE_PCIE_2_CFG 684
|
||||
#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
|
||||
#define MSM_BUS_SLAVE_A0NOC_CFG 686
|
||||
#define MSM_BUS_SLAVE_A1NOC_CFG 687
|
||||
#define MSM_BUS_SLAVE_A2NOC_CFG 688
|
||||
#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
|
||||
#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
|
||||
#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
|
||||
#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
|
||||
#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
|
||||
#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
|
||||
#define MSM_BUS_SLAVE_MMAGIC_CFG 695
|
||||
#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
|
||||
#define MSM_BUS_SLAVE_SSC_CFG 697
|
||||
#define MSM_BUS_SLAVE_DSA_CFG 698
|
||||
#define MSM_BUS_SLAVE_DSA_MPU_CFG 699
|
||||
#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
|
||||
#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701
|
||||
#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
|
||||
#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703
|
||||
#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
|
||||
#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
|
||||
#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706
|
||||
#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
|
||||
#define MSM_BUS_SLAVE_VMEM_CFG 708
|
||||
#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709
|
||||
#define MSM_BUS_SLAVE_VMEM 710
|
||||
#define MSM_BUS_SLAVE_AHB2PHY 711
|
||||
#define MSM_BUS_SLAVE_PIMEM 712
|
||||
#define MSM_BUS_SLAVE_SNOC_VMEM 713
|
||||
#define MSM_BUS_SLAVE_PCIE_2 714
|
||||
#define MSM_BUS_SLAVE_RBCPR_MX 715
|
||||
#define MSM_BUS_SLAVE_RBCPR_CX 716
|
||||
#define MSM_BUS_SLAVE_BIMC_PCNOC 717
|
||||
#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718
|
||||
#define MSM_BUS_SLAVE_SGMII 719
|
||||
#define MSM_BUS_SLAVE_SPMI_FETCHER 720
|
||||
#define MSM_BUS_PNOC_SLV_6 721
|
||||
#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722
|
||||
#define MSM_BUS_SLAVE_WLAN 723
|
||||
#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724
|
||||
#define MSM_BUS_SLAVE_CNOC_A2NOC 725
|
||||
#define MSM_BUS_SLAVE_GLM 726
|
||||
#define MSM_BUS_SLAVE_GNOC_BIMC 727
|
||||
#define MSM_BUS_SLAVE_GNOC_SNOC 728
|
||||
#define MSM_BUS_SLAVE_QM_CFG 729
|
||||
#define MSM_BUS_SLAVE_TLMM_EAST 730
|
||||
#define MSM_BUS_SLAVE_TLMM_NORTH 731
|
||||
#define MSM_BUS_SLAVE_TLMM_WEST 732
|
||||
#define MSM_BUS_SLAVE_SKL 733
|
||||
#define MSM_BUS_SLAVE_LPASS_TCM 734
|
||||
#define MSM_BUS_SLAVE_TLMM_SOUTH 735
|
||||
#define MSM_BUS_SLAVE_TLMM_CENTER 736
|
||||
#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737
|
||||
#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738
|
||||
#define MSM_BUS_SLAVE_CDSP 739
|
||||
#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740
|
||||
#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741
|
||||
#define MSM_BUS_SLAVE_CSI_PHY_CFG 742
|
||||
#define MSM_BUS_SLAVE_LAST 743
|
||||
|
||||
#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
|
||||
#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
|
||||
|
||||
/*
|
||||
* ID's used in RPM messages
|
||||
*/
|
||||
#define ICBID_MASTER_APPSS_PROC 0
|
||||
#define ICBID_MASTER_MSS_PROC 1
|
||||
#define ICBID_MASTER_MNOC_BIMC 2
|
||||
#define ICBID_MASTER_SNOC_BIMC 3
|
||||
#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
|
||||
#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
|
||||
#define ICBID_MASTER_CNOC_MNOC_CFG 5
|
||||
#define ICBID_MASTER_GFX3D 6
|
||||
#define ICBID_MASTER_JPEG 7
|
||||
#define ICBID_MASTER_MDP 8
|
||||
#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
|
||||
#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
|
||||
#define ICBID_MASTER_VIDEO 9
|
||||
#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
|
||||
#define ICBID_MASTER_VIDEO_P1 10
|
||||
#define ICBID_MASTER_VFE 11
|
||||
#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE
|
||||
#define ICBID_MASTER_CNOC_ONOC_CFG 12
|
||||
#define ICBID_MASTER_JPEG_OCMEM 13
|
||||
#define ICBID_MASTER_MDP_OCMEM 14
|
||||
#define ICBID_MASTER_VIDEO_P0_OCMEM 15
|
||||
#define ICBID_MASTER_VIDEO_P1_OCMEM 16
|
||||
#define ICBID_MASTER_VFE_OCMEM 17
|
||||
#define ICBID_MASTER_LPASS_AHB 18
|
||||
#define ICBID_MASTER_QDSS_BAM 19
|
||||
#define ICBID_MASTER_SNOC_CFG 20
|
||||
#define ICBID_MASTER_BIMC_SNOC 21
|
||||
#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC
|
||||
#define ICBID_MASTER_CNOC_SNOC 22
|
||||
#define ICBID_MASTER_CRYPTO 23
|
||||
#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
|
||||
#define ICBID_MASTER_CRYPTO_CORE1 24
|
||||
#define ICBID_MASTER_LPASS_PROC 25
|
||||
#define ICBID_MASTER_MSS 26
|
||||
#define ICBID_MASTER_MSS_NAV 27
|
||||
#define ICBID_MASTER_OCMEM_DMA 28
|
||||
#define ICBID_MASTER_PNOC_SNOC 29
|
||||
#define ICBID_MASTER_WCSS 30
|
||||
#define ICBID_MASTER_QDSS_ETR 31
|
||||
#define ICBID_MASTER_USB3 32
|
||||
#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
|
||||
#define ICBID_MASTER_SDCC_1 33
|
||||
#define ICBID_MASTER_SDCC_3 34
|
||||
#define ICBID_MASTER_SDCC_2 35
|
||||
#define ICBID_MASTER_SDCC_4 36
|
||||
#define ICBID_MASTER_TSIF 37
|
||||
#define ICBID_MASTER_BAM_DMA 38
|
||||
#define ICBID_MASTER_BLSP_2 39
|
||||
#define ICBID_MASTER_USB_HSIC 40
|
||||
#define ICBID_MASTER_BLSP_1 41
|
||||
#define ICBID_MASTER_USB_HS 42
|
||||
#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
|
||||
#define ICBID_MASTER_PNOC_CFG 43
|
||||
#define ICBID_MASTER_SNOC_PNOC 44
|
||||
#define ICBID_MASTER_RPM_INST 45
|
||||
#define ICBID_MASTER_RPM_DATA 46
|
||||
#define ICBID_MASTER_RPM_SYS 47
|
||||
#define ICBID_MASTER_DEHR 48
|
||||
#define ICBID_MASTER_QDSS_DAP 49
|
||||
#define ICBID_MASTER_SPDM 50
|
||||
#define ICBID_MASTER_TIC 51
|
||||
#define ICBID_MASTER_SNOC_CNOC 52
|
||||
#define ICBID_MASTER_GFX3D_OCMEM 53
|
||||
#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
|
||||
#define ICBID_MASTER_OVIRT_SNOC 54
|
||||
#define ICBID_MASTER_SNOC_OVIRT 55
|
||||
#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
|
||||
#define ICBID_MASTER_ONOC_OVIRT 56
|
||||
#define ICBID_MASTER_USB_HS2 57
|
||||
#define ICBID_MASTER_QPIC 58
|
||||
#define ICBID_MASTER_IPA 59
|
||||
#define ICBID_MASTER_DSI 60
|
||||
#define ICBID_MASTER_MDP1 61
|
||||
#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
|
||||
#define ICBID_MASTER_VPU_PROC 62
|
||||
#define ICBID_MASTER_VPU 63
|
||||
#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
|
||||
#define ICBID_MASTER_CRYPTO_CORE2 64
|
||||
#define ICBID_MASTER_PCIE_0 65
|
||||
#define ICBID_MASTER_PCIE_1 66
|
||||
#define ICBID_MASTER_SATA 67
|
||||
#define ICBID_MASTER_UFS 68
|
||||
#define ICBID_MASTER_USB3_1 69
|
||||
#define ICBID_MASTER_VIDEO_OCMEM 70
|
||||
#define ICBID_MASTER_VPU1 71
|
||||
#define ICBID_MASTER_VCAP 72
|
||||
#define ICBID_MASTER_EMAC 73
|
||||
#define ICBID_MASTER_BCAST 74
|
||||
#define ICBID_MASTER_MMSS_PROC 75
|
||||
#define ICBID_MASTER_SNOC_BIMC_1 76
|
||||
#define ICBID_MASTER_SNOC_PCNOC 77
|
||||
#define ICBID_MASTER_AUDIO 78
|
||||
#define ICBID_MASTER_MM_INT_0 79
|
||||
#define ICBID_MASTER_MM_INT_1 80
|
||||
#define ICBID_MASTER_MM_INT_2 81
|
||||
#define ICBID_MASTER_MM_INT_BIMC 82
|
||||
#define ICBID_MASTER_MSS_INT 83
|
||||
#define ICBID_MASTER_PCNOC_CFG 84
|
||||
#define ICBID_MASTER_PCNOC_INT_0 85
|
||||
#define ICBID_MASTER_PCNOC_INT_1 86
|
||||
#define ICBID_MASTER_PCNOC_M_0 87
|
||||
#define ICBID_MASTER_PCNOC_M_1 88
|
||||
#define ICBID_MASTER_PCNOC_S_0 89
|
||||
#define ICBID_MASTER_PCNOC_S_1 90
|
||||
#define ICBID_MASTER_PCNOC_S_2 91
|
||||
#define ICBID_MASTER_PCNOC_S_3 92
|
||||
#define ICBID_MASTER_PCNOC_S_4 93
|
||||
#define ICBID_MASTER_PCNOC_S_6 94
|
||||
#define ICBID_MASTER_PCNOC_S_7 95
|
||||
#define ICBID_MASTER_PCNOC_S_8 96
|
||||
#define ICBID_MASTER_PCNOC_S_9 97
|
||||
#define ICBID_MASTER_QDSS_INT 98
|
||||
#define ICBID_MASTER_SNOC_INT_0 99
|
||||
#define ICBID_MASTER_SNOC_INT_1 100
|
||||
#define ICBID_MASTER_SNOC_INT_BIMC 101
|
||||
#define ICBID_MASTER_TCU_0 102
|
||||
#define ICBID_MASTER_TCU_1 103
|
||||
#define ICBID_MASTER_BIMC_INT_0 104
|
||||
#define ICBID_MASTER_BIMC_INT_1 105
|
||||
#define ICBID_MASTER_CAMERA 106
|
||||
#define ICBID_MASTER_RICA 107
|
||||
#define ICBID_MASTER_SNOC_BIMC_2 108
|
||||
#define ICBID_MASTER_BIMC_SNOC_1 109
|
||||
#define ICBID_MASTER_A0NOC_SNOC 110
|
||||
#define ICBID_MASTER_A1NOC_SNOC 111
|
||||
#define ICBID_MASTER_A2NOC_SNOC 112
|
||||
#define ICBID_MASTER_PIMEM 113
|
||||
#define ICBID_MASTER_SNOC_VMEM 114
|
||||
#define ICBID_MASTER_CPP 115
|
||||
#define ICBID_MASTER_CNOC_A1NOC 116
|
||||
#define ICBID_MASTER_PNOC_A1NOC 117
|
||||
#define ICBID_MASTER_HMSS 118
|
||||
#define ICBID_MASTER_PCIE_2 119
|
||||
#define ICBID_MASTER_ROTATOR 120
|
||||
#define ICBID_MASTER_VENUS_VMEM 121
|
||||
#define ICBID_MASTER_DCC 122
|
||||
#define ICBID_MASTER_MCDMA 123
|
||||
#define ICBID_MASTER_PCNOC_INT_2 124
|
||||
#define ICBID_MASTER_PCNOC_INT_3 125
|
||||
#define ICBID_MASTER_PCNOC_INT_4 126
|
||||
#define ICBID_MASTER_PCNOC_INT_5 127
|
||||
#define ICBID_MASTER_PCNOC_INT_6 128
|
||||
#define ICBID_MASTER_PCNOC_S_5 129
|
||||
#define ICBID_MASTER_SENSORS_AHB 130
|
||||
#define ICBID_MASTER_SENSORS_PROC 131
|
||||
#define ICBID_MASTER_QSPI 132
|
||||
#define ICBID_MASTER_VFE1 133
|
||||
#define ICBID_MASTER_SNOC_INT_2 134
|
||||
#define ICBID_MASTER_SMMNOC_BIMC 135
|
||||
#define ICBID_MASTER_CRVIRT_A1NOC 136
|
||||
#define ICBID_MASTER_XM_USB_HS1 137
|
||||
#define ICBID_MASTER_XI_USB_HS1 138
|
||||
#define ICBID_MASTER_PCNOC_BIMC_1 139
|
||||
#define ICBID_MASTER_BIMC_PCNOC 140
|
||||
#define ICBID_MASTER_XI_HSIC 141
|
||||
#define ICBID_MASTER_SGMII 142
|
||||
#define ICBID_MASTER_SPMI_FETCHER 143
|
||||
#define ICBID_MASTER_GNOC_BIMC 144
|
||||
#define ICBID_MASTER_CRVIRT_A2NOC 145
|
||||
#define ICBID_MASTER_CNOC_A2NOC 146
|
||||
#define ICBID_MASTER_WLAN 147
|
||||
#define ICBID_MASTER_MSS_CE 148
|
||||
#define ICBID_MASTER_CDSP_PROC 149
|
||||
#define ICBID_MASTER_GNOC_SNOC 150
|
||||
|
||||
#define ICBID_SLAVE_EBI1 0
|
||||
#define ICBID_SLAVE_APPSS_L2 1
|
||||
#define ICBID_SLAVE_BIMC_SNOC 2
|
||||
#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC
|
||||
#define ICBID_SLAVE_CAMERA_CFG 3
|
||||
#define ICBID_SLAVE_DISPLAY_CFG 4
|
||||
#define ICBID_SLAVE_OCMEM_CFG 5
|
||||
#define ICBID_SLAVE_CPR_CFG 6
|
||||
#define ICBID_SLAVE_CPR_XPU_CFG 7
|
||||
#define ICBID_SLAVE_MISC_CFG 8
|
||||
#define ICBID_SLAVE_MISC_XPU_CFG 9
|
||||
#define ICBID_SLAVE_VENUS_CFG 10
|
||||
#define ICBID_SLAVE_GFX3D_CFG 11
|
||||
#define ICBID_SLAVE_MMSS_CLK_CFG 12
|
||||
#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
|
||||
#define ICBID_SLAVE_MNOC_MPU_CFG 14
|
||||
#define ICBID_SLAVE_ONOC_MPU_CFG 15
|
||||
#define ICBID_SLAVE_MNOC_BIMC 16
|
||||
#define ICBID_SLAVE_SERVICE_MNOC 17
|
||||
#define ICBID_SLAVE_OCMEM 18
|
||||
#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
|
||||
#define ICBID_SLAVE_SERVICE_ONOC 19
|
||||
#define ICBID_SLAVE_APPSS 20
|
||||
#define ICBID_SLAVE_LPASS 21
|
||||
#define ICBID_SLAVE_USB3 22
|
||||
#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
|
||||
#define ICBID_SLAVE_WCSS 23
|
||||
#define ICBID_SLAVE_SNOC_BIMC 24
|
||||
#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
|
||||
#define ICBID_SLAVE_SNOC_CNOC 25
|
||||
#define ICBID_SLAVE_IMEM 26
|
||||
#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
|
||||
#define ICBID_SLAVE_SNOC_OVIRT 27
|
||||
#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
|
||||
#define ICBID_SLAVE_SNOC_PNOC 28
|
||||
#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
|
||||
#define ICBID_SLAVE_SERVICE_SNOC 29
|
||||
#define ICBID_SLAVE_QDSS_STM 30
|
||||
#define ICBID_SLAVE_SDCC_1 31
|
||||
#define ICBID_SLAVE_SDCC_3 32
|
||||
#define ICBID_SLAVE_SDCC_2 33
|
||||
#define ICBID_SLAVE_SDCC_4 34
|
||||
#define ICBID_SLAVE_TSIF 35
|
||||
#define ICBID_SLAVE_BAM_DMA 36
|
||||
#define ICBID_SLAVE_BLSP_2 37
|
||||
#define ICBID_SLAVE_USB_HSIC 38
|
||||
#define ICBID_SLAVE_BLSP_1 39
|
||||
#define ICBID_SLAVE_USB_HS 40
|
||||
#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
|
||||
#define ICBID_SLAVE_PDM 41
|
||||
#define ICBID_SLAVE_PERIPH_APU_CFG 42
|
||||
#define ICBID_SLAVE_PNOC_MPU_CFG 43
|
||||
#define ICBID_SLAVE_PRNG 44
|
||||
#define ICBID_SLAVE_PNOC_SNOC 45
|
||||
#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
|
||||
#define ICBID_SLAVE_SERVICE_PNOC 46
|
||||
#define ICBID_SLAVE_CLK_CTL 47
|
||||
#define ICBID_SLAVE_CNOC_MSS 48
|
||||
#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
|
||||
#define ICBID_SLAVE_SECURITY 49
|
||||
#define ICBID_SLAVE_TCSR 50
|
||||
#define ICBID_SLAVE_TLMM 51
|
||||
#define ICBID_SLAVE_CRYPTO_0_CFG 52
|
||||
#define ICBID_SLAVE_CRYPTO_1_CFG 53
|
||||
#define ICBID_SLAVE_IMEM_CFG 54
|
||||
#define ICBID_SLAVE_MESSAGE_RAM 55
|
||||
#define ICBID_SLAVE_BIMC_CFG 56
|
||||
#define ICBID_SLAVE_BOOT_ROM 57
|
||||
#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
|
||||
#define ICBID_SLAVE_PMIC_ARB 59
|
||||
#define ICBID_SLAVE_SPDM_WRAPPER 60
|
||||
#define ICBID_SLAVE_DEHR_CFG 61
|
||||
#define ICBID_SLAVE_MPM 62
|
||||
#define ICBID_SLAVE_QDSS_CFG 63
|
||||
#define ICBID_SLAVE_RBCPR_CFG 64
|
||||
#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
|
||||
#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
|
||||
#define ICBID_SLAVE_CNOC_MNOC_CFG 66
|
||||
#define ICBID_SLAVE_SNOC_MPU_CFG 67
|
||||
#define ICBID_SLAVE_CNOC_ONOC_CFG 68
|
||||
#define ICBID_SLAVE_PNOC_CFG 69
|
||||
#define ICBID_SLAVE_SNOC_CFG 70
|
||||
#define ICBID_SLAVE_EBI1_DLL_CFG 71
|
||||
#define ICBID_SLAVE_PHY_APU_CFG 72
|
||||
#define ICBID_SLAVE_EBI1_PHY_CFG 73
|
||||
#define ICBID_SLAVE_RPM 74
|
||||
#define ICBID_SLAVE_CNOC_SNOC 75
|
||||
#define ICBID_SLAVE_SERVICE_CNOC 76
|
||||
#define ICBID_SLAVE_OVIRT_SNOC 77
|
||||
#define ICBID_SLAVE_OVIRT_OCMEM 78
|
||||
#define ICBID_SLAVE_USB_HS2 79
|
||||
#define ICBID_SLAVE_QPIC 80
|
||||
#define ICBID_SLAVE_IPS_CFG 81
|
||||
#define ICBID_SLAVE_DSI_CFG 82
|
||||
#define ICBID_SLAVE_USB3_1 83
|
||||
#define ICBID_SLAVE_PCIE_0 84
|
||||
#define ICBID_SLAVE_PCIE_1 85
|
||||
#define ICBID_SLAVE_PSS_SMMU_CFG 86
|
||||
#define ICBID_SLAVE_CRYPTO_2_CFG 87
|
||||
#define ICBID_SLAVE_PCIE_0_CFG 88
|
||||
#define ICBID_SLAVE_PCIE_1_CFG 89
|
||||
#define ICBID_SLAVE_SATA_CFG 90
|
||||
#define ICBID_SLAVE_SPSS_GENI_IR 91
|
||||
#define ICBID_SLAVE_UFS_CFG 92
|
||||
#define ICBID_SLAVE_AVSYNC_CFG 93
|
||||
#define ICBID_SLAVE_VPU_CFG 94
|
||||
#define ICBID_SLAVE_USB_PHY_CFG 95
|
||||
#define ICBID_SLAVE_RBCPR_MX_CFG 96
|
||||
#define ICBID_SLAVE_PCIE_PARF 97
|
||||
#define ICBID_SLAVE_VCAP_CFG 98
|
||||
#define ICBID_SLAVE_EMAC_CFG 99
|
||||
#define ICBID_SLAVE_BCAST_CFG 100
|
||||
#define ICBID_SLAVE_KLM_CFG 101
|
||||
#define ICBID_SLAVE_DISPLAY_PWM 102
|
||||
#define ICBID_SLAVE_GENI 103
|
||||
#define ICBID_SLAVE_SNOC_BIMC_1 104
|
||||
#define ICBID_SLAVE_AUDIO 105
|
||||
#define ICBID_SLAVE_CATS_0 106
|
||||
#define ICBID_SLAVE_CATS_1 107
|
||||
#define ICBID_SLAVE_MM_INT_0 108
|
||||
#define ICBID_SLAVE_MM_INT_1 109
|
||||
#define ICBID_SLAVE_MM_INT_2 110
|
||||
#define ICBID_SLAVE_MM_INT_BIMC 111
|
||||
#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
|
||||
#define ICBID_SLAVE_MSS_INT 113
|
||||
#define ICBID_SLAVE_PCNOC_INT_0 114
|
||||
#define ICBID_SLAVE_PCNOC_INT_1 115
|
||||
#define ICBID_SLAVE_PCNOC_M_0 116
|
||||
#define ICBID_SLAVE_PCNOC_M_1 117
|
||||
#define ICBID_SLAVE_PCNOC_S_0 118
|
||||
#define ICBID_SLAVE_PCNOC_S_1 119
|
||||
#define ICBID_SLAVE_PCNOC_S_2 120
|
||||
#define ICBID_SLAVE_PCNOC_S_3 121
|
||||
#define ICBID_SLAVE_PCNOC_S_4 122
|
||||
#define ICBID_SLAVE_PCNOC_S_6 123
|
||||
#define ICBID_SLAVE_PCNOC_S_7 124
|
||||
#define ICBID_SLAVE_PCNOC_S_8 125
|
||||
#define ICBID_SLAVE_PCNOC_S_9 126
|
||||
#define ICBID_SLAVE_PRNG_XPU_CFG 127
|
||||
#define ICBID_SLAVE_QDSS_INT 128
|
||||
#define ICBID_SLAVE_RPM_XPU_CFG 129
|
||||
#define ICBID_SLAVE_SNOC_INT_0 130
|
||||
#define ICBID_SLAVE_SNOC_INT_1 131
|
||||
#define ICBID_SLAVE_SNOC_INT_BIMC 132
|
||||
#define ICBID_SLAVE_TCU 133
|
||||
#define ICBID_SLAVE_BIMC_INT_0 134
|
||||
#define ICBID_SLAVE_BIMC_INT_1 135
|
||||
#define ICBID_SLAVE_RICA_CFG 136
|
||||
#define ICBID_SLAVE_SNOC_BIMC_2 137
|
||||
#define ICBID_SLAVE_BIMC_SNOC_1 138
|
||||
#define ICBID_SLAVE_PNOC_A1NOC 139
|
||||
#define ICBID_SLAVE_SNOC_VMEM 140
|
||||
#define ICBID_SLAVE_A0NOC_SNOC 141
|
||||
#define ICBID_SLAVE_A1NOC_SNOC 142
|
||||
#define ICBID_SLAVE_A2NOC_SNOC 143
|
||||
#define ICBID_SLAVE_A0NOC_CFG 144
|
||||
#define ICBID_SLAVE_A0NOC_MPU_CFG 145
|
||||
#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
|
||||
#define ICBID_SLAVE_A1NOC_CFG 147
|
||||
#define ICBID_SLAVE_A1NOC_MPU_CFG 148
|
||||
#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
|
||||
#define ICBID_SLAVE_A2NOC_CFG 150
|
||||
#define ICBID_SLAVE_A2NOC_MPU_CFG 151
|
||||
#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
|
||||
#define ICBID_SLAVE_AHB2PHY 153
|
||||
#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
|
||||
#define ICBID_SLAVE_DCC_CFG 155
|
||||
#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
|
||||
#define ICBID_SLAVE_DSA_CFG 157
|
||||
#define ICBID_SLAVE_DSA_MPU_CFG 158
|
||||
#define ICBID_SLAVE_SSC_MPU_CFG 159
|
||||
#define ICBID_SLAVE_HMSS_L3 160
|
||||
#define ICBID_SLAVE_LPASS_SMMU_CFG 161
|
||||
#define ICBID_SLAVE_MMAGIC_CFG 162
|
||||
#define ICBID_SLAVE_PCIE20_AHB2PHY 163
|
||||
#define ICBID_SLAVE_PCIE_2 164
|
||||
#define ICBID_SLAVE_PCIE_2_CFG 165
|
||||
#define ICBID_SLAVE_PIMEM 166
|
||||
#define ICBID_SLAVE_PIMEM_CFG 167
|
||||
#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
|
||||
#define ICBID_SLAVE_RBCPR_CX 169
|
||||
#define ICBID_SLAVE_RBCPR_MX 170
|
||||
#define ICBID_SLAVE_SMMU_CPP_CFG 171
|
||||
#define ICBID_SLAVE_SMMU_JPEG_CFG 172
|
||||
#define ICBID_SLAVE_SMMU_MDP_CFG 173
|
||||
#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
|
||||
#define ICBID_SLAVE_SMMU_VENUS_CFG 175
|
||||
#define ICBID_SLAVE_SMMU_VFE_CFG 176
|
||||
#define ICBID_SLAVE_SSC_CFG 177
|
||||
#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
|
||||
#define ICBID_SLAVE_VMEM 179
|
||||
#define ICBID_SLAVE_VMEM_CFG 180
|
||||
#define ICBID_SLAVE_QDSS_MPU_CFG 181
|
||||
#define ICBID_SLAVE_USB3_PHY_CFG 182
|
||||
#define ICBID_SLAVE_IPA_CFG 183
|
||||
#define ICBID_SLAVE_PCNOC_INT_2 184
|
||||
#define ICBID_SLAVE_PCNOC_INT_3 185
|
||||
#define ICBID_SLAVE_PCNOC_INT_4 186
|
||||
#define ICBID_SLAVE_PCNOC_INT_5 187
|
||||
#define ICBID_SLAVE_PCNOC_INT_6 188
|
||||
#define ICBID_SLAVE_PCNOC_S_5 189
|
||||
#define ICBID_SLAVE_QSPI 190
|
||||
#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191
|
||||
#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192
|
||||
#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193
|
||||
#define ICBID_SLAVE_MSS_MPU_CFG 194
|
||||
#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195
|
||||
#define ICBID_SLAVE_SKL 196
|
||||
#define ICBID_SLAVE_SNOC_INT_2 197
|
||||
#define ICBID_SLAVE_SMMNOC_BIMC 198
|
||||
#define ICBID_SLAVE_CRVIRT_A1NOC 199
|
||||
#define ICBID_SLAVE_SGMII 200
|
||||
#define ICBID_SLAVE_QHS4_APPS 201
|
||||
#define ICBID_SLAVE_BIMC_PCNOC 202
|
||||
#define ICBID_SLAVE_PCNOC_BIMC_1 203
|
||||
#define ICBID_SLAVE_SPMI_FETCHER 204
|
||||
#define ICBID_SLAVE_MMSS_SMMU_CFG 205
|
||||
#define ICBID_SLAVE_WLAN 206
|
||||
#define ICBID_SLAVE_CRVIRT_A2NOC 207
|
||||
#define ICBID_SLAVE_CNOC_A2NOC 208
|
||||
#define ICBID_SLAVE_GLM 209
|
||||
#define ICBID_SLAVE_GNOC_BIMC 210
|
||||
#define ICBID_SLAVE_GNOC_SNOC 211
|
||||
#define ICBID_SLAVE_QM_CFG 212
|
||||
#define ICBID_SLAVE_TLMM_EAST 213
|
||||
#define ICBID_SLAVE_TLMM_NORTH 214
|
||||
#define ICBID_SLAVE_TLMM_WEST 215
|
||||
#define ICBID_SLAVE_LPASS_TCM 216
|
||||
#define ICBID_SLAVE_TLMM_SOUTH 217
|
||||
#define ICBID_SLAVE_TLMM_CENTER 218
|
||||
#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219
|
||||
#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220
|
||||
#define ICBID_SLAVE_CDSP 221
|
||||
#define ICBID_SLAVE_CDSP_SMMU_CFG 222
|
||||
#define ICBID_SLAVE_LPASS_MPU_CFG 223
|
||||
#define ICBID_SLAVE_CSI_PHY_CFG 224
|
||||
#endif
|
||||
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Reference in New Issue