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clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling 

[ Upstream commit 1a500e0bc9 ]

On SM8350 platform the PCIe PIPE clocks require additional handling to
function correctly. They are to be switched to the tcxo source before
turning PCIe GDSCs off and should be switched to PHY PIPE source once
they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops,
which provide support for this dance.

Fixes: 44c20c9ed3 ("clk: qcom: gcc: Add clock driver for SM8350")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2023-04-12 16:48:29 +03:00 committed by Greg Kroah-Hartman
parent b75450f51c
commit c3d4119fa5
1 changed files with 13 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
drivers/clk/qcom/gcc-sm8350.c
View File

@ -17,6 +17,7 @@
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
@ -167,26 +168,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_PCIE_0_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "pcie_0_pipe_clk", },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_PCIE_1_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "pcie_1_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@ -289,32 +270,30 @@ static const struct clk_parent_data gcc_parent_data_14[] = {
{ .fw_name = "bi_tcxo" },
};
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b054,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d054,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_5,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};