phy: ti: am654: simplify regfield handling
regfield handling in current driver code is made complicated by having a separate regfield variable for each field which is allocated individually. This quickly gets unwieldy once number of regfields increase. Instead, use an array of regfields which are allocated in a loop. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200727194603.44636-2-nsekhar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sekhar Nori
Vinod Koul
parent
a85643d47d
commit
c3e60e5a9e
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@ -22,7 +22,7 @@
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#define CMU_R07C 0x7c
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#define COMLANE_R138 0xb38
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#define VERSION 0x70
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#define VERSION_VAL 0x70
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#define COMLANE_R190 0xb90
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@ -80,27 +80,52 @@ static const struct regmap_config serdes_am654_regmap_config = {
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.max_register = 0x1ffc,
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};
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static const struct reg_field cmu_master_cdn_o = REG_FIELD(CMU_R07C, 24, 24);
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static const struct reg_field config_version = REG_FIELD(COMLANE_R138, 16, 23);
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static const struct reg_field l1_master_cdn_o = REG_FIELD(COMLANE_R190, 9, 9);
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static const struct reg_field cmu_ok_i_0 = REG_FIELD(COMLANE_R194, 19, 19);
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static const struct reg_field por_en = REG_FIELD(SERDES_CTRL, 29, 29);
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static const struct reg_field tx0_enable = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31);
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static const struct reg_field rx0_enable = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15);
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static const struct reg_field pll_enable = REG_FIELD(WIZ_PLL_CTRL, 29, 31);
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static const struct reg_field pll_ok = REG_FIELD(WIZ_PLL_CTRL, 28, 28);
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enum serdes_am654_fields {
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/* CMU Master Reset */
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CMU_MASTER_CDN,
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CONFIG_VERSION,
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/* Lane 1 Master Reset */
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L1_MASTER_CDN,
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/* CMU OK Status */
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CMU_OK_I_0,
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/* Serdes reset */
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POR_EN,
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/* Tx Enable Value */
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TX0_ENABLE,
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/* Rx Enable Value */
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RX0_ENABLE,
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/* PLL Enable Value */
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PLL_ENABLE,
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/* PLL ready for use */
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PLL_OK,
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/* sentinel */
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MAX_FIELDS
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};
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static const struct reg_field serdes_am654_reg_fields[] = {
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[CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 24),
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[CONFIG_VERSION] = REG_FIELD(COMLANE_R138, 16, 23),
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[L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 9, 9),
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[CMU_OK_I_0] = REG_FIELD(COMLANE_R194, 19, 19),
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[POR_EN] = REG_FIELD(SERDES_CTRL, 29, 29),
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[TX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31),
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[RX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15),
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[PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
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[PLL_OK] = REG_FIELD(WIZ_PLL_CTRL, 28, 28),
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};
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struct serdes_am654 {
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struct regmap *regmap;
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struct regmap_field *cmu_master_cdn_o;
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struct regmap_field *config_version;
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struct regmap_field *l1_master_cdn_o;
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struct regmap_field *cmu_ok_i_0;
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struct regmap_field *por_en;
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struct regmap_field *tx0_enable;
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struct regmap_field *rx0_enable;
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struct regmap_field *pll_enable;
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struct regmap_field *pll_ok;
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struct regmap_field *fields[MAX_FIELDS];
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struct device *dev;
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struct mux_control *control;
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@ -116,12 +141,12 @@ static int serdes_am654_enable_pll(struct serdes_am654 *phy)
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int ret;
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u32 val;
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ret = regmap_field_write(phy->pll_enable, PLL_ENABLE_STATE);
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ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
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if (ret)
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return ret;
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return regmap_field_read_poll_timeout(phy->pll_ok, val, val, 1000,
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PLL_LOCK_TIME);
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return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,
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1000, PLL_LOCK_TIME);
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}
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static void serdes_am654_disable_pll(struct serdes_am654 *phy)
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@ -129,7 +154,7 @@ static void serdes_am654_disable_pll(struct serdes_am654 *phy)
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struct device *dev = phy->dev;
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int ret;
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ret = regmap_field_write(phy->pll_enable, PLL_DISABLE_STATE);
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ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
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if (ret)
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dev_err(dev, "Failed to disable PLL\n");
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}
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@ -139,12 +164,12 @@ static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
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int ret;
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/* Enable TX */
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ret = regmap_field_write(phy->tx0_enable, TX0_ENABLE_STATE);
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ret = regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);
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if (ret)
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return ret;
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/* Enable RX */
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ret = regmap_field_write(phy->rx0_enable, RX0_ENABLE_STATE);
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ret = regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);
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if (ret)
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return ret;
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@ -156,12 +181,12 @@ static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
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int ret;
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/* Disable TX */
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ret = regmap_field_write(phy->tx0_enable, TX0_DISABLE_STATE);
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ret = regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);
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if (ret)
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return ret;
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/* Disable RX */
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ret = regmap_field_write(phy->rx0_enable, RX0_DISABLE_STATE);
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ret = regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);
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if (ret)
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return ret;
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@ -187,8 +212,8 @@ static int serdes_am654_power_on(struct phy *x)
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return ret;
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}
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return regmap_field_read_poll_timeout(phy->cmu_ok_i_0, val, val,
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SLEEP_TIME, PLL_LOCK_TIME);
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return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,
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val, SLEEP_TIME, PLL_LOCK_TIME);
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}
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static int serdes_am654_power_off(struct phy *x)
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@ -288,15 +313,15 @@ static int serdes_am654_pcie_init(struct serdes_am654 *phy)
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{
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int ret;
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ret = regmap_field_write(phy->config_version, VERSION);
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ret = regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
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if (ret)
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return ret;
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ret = regmap_field_write(phy->cmu_master_cdn_o, 0x1);
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ret = regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
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if (ret)
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return ret;
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ret = regmap_field_write(phy->l1_master_cdn_o, 0x1);
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ret = regmap_field_write(phy->fields[L1_MASTER_CDN], 0x1);
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if (ret)
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return ret;
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@ -325,13 +350,13 @@ static int serdes_am654_reset(struct phy *x)
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serdes_am654_disable_pll(phy);
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serdes_am654_disable_txrx(phy);
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ret = regmap_field_write(phy->por_en, 0x1);
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ret = regmap_field_write(phy->fields[POR_EN], 0x1);
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if (ret)
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return ret;
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mdelay(1);
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ret = regmap_field_write(phy->por_en, 0x0);
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ret = regmap_field_write(phy->fields[POR_EN], 0x0);
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if (ret)
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return ret;
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@ -587,66 +612,16 @@ static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
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{
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struct regmap *regmap = am654_phy->regmap;
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struct device *dev = am654_phy->dev;
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int i;
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am654_phy->cmu_master_cdn_o = devm_regmap_field_alloc(dev, regmap,
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cmu_master_cdn_o);
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if (IS_ERR(am654_phy->cmu_master_cdn_o)) {
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dev_err(dev, "CMU_MASTER_CDN_O reg field init failed\n");
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return PTR_ERR(am654_phy->cmu_master_cdn_o);
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}
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am654_phy->config_version = devm_regmap_field_alloc(dev, regmap,
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config_version);
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if (IS_ERR(am654_phy->config_version)) {
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dev_err(dev, "CONFIG_VERSION reg field init failed\n");
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return PTR_ERR(am654_phy->config_version);
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}
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am654_phy->l1_master_cdn_o = devm_regmap_field_alloc(dev, regmap,
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l1_master_cdn_o);
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if (IS_ERR(am654_phy->l1_master_cdn_o)) {
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dev_err(dev, "L1_MASTER_CDN_O reg field init failed\n");
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return PTR_ERR(am654_phy->l1_master_cdn_o);
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}
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am654_phy->cmu_ok_i_0 = devm_regmap_field_alloc(dev, regmap,
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cmu_ok_i_0);
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if (IS_ERR(am654_phy->cmu_ok_i_0)) {
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dev_err(dev, "CMU_OK_I_0 reg field init failed\n");
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return PTR_ERR(am654_phy->cmu_ok_i_0);
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}
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am654_phy->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
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if (IS_ERR(am654_phy->por_en)) {
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dev_err(dev, "POR_EN reg field init failed\n");
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return PTR_ERR(am654_phy->por_en);
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}
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am654_phy->tx0_enable = devm_regmap_field_alloc(dev, regmap,
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tx0_enable);
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if (IS_ERR(am654_phy->tx0_enable)) {
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dev_err(dev, "TX0_ENABLE reg field init failed\n");
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return PTR_ERR(am654_phy->tx0_enable);
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}
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am654_phy->rx0_enable = devm_regmap_field_alloc(dev, regmap,
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rx0_enable);
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if (IS_ERR(am654_phy->rx0_enable)) {
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dev_err(dev, "RX0_ENABLE reg field init failed\n");
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return PTR_ERR(am654_phy->rx0_enable);
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}
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am654_phy->pll_enable = devm_regmap_field_alloc(dev, regmap,
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pll_enable);
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if (IS_ERR(am654_phy->pll_enable)) {
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dev_err(dev, "PLL_ENABLE reg field init failed\n");
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return PTR_ERR(am654_phy->pll_enable);
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}
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am654_phy->pll_ok = devm_regmap_field_alloc(dev, regmap, pll_ok);
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if (IS_ERR(am654_phy->pll_ok)) {
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dev_err(dev, "PLL_OK reg field init failed\n");
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return PTR_ERR(am654_phy->pll_ok);
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for (i = 0; i < MAX_FIELDS; i++) {
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am654_phy->fields[i] = devm_regmap_field_alloc(dev,
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regmap,
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serdes_am654_reg_fields[i]);
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if (IS_ERR(am654_phy->fields[i])) {
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dev_err(dev, "Unable to allocate regmap field %d\n", i);
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return PTR_ERR(am654_phy->fields[i]);
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}
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}
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return 0;
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