mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
Merge tag 'drm-intel-next-fixes-2016-07-25' of git://anongit.freedesktop.org/drm-intel into drm-next
Bunch of fixes for the 4.8 merge pull, nothing out of the ordinary. All suitably marked up with cc: stable where needed. * tag 'drm-intel-next-fixes-2016-07-25' of git://anongit.freedesktop.org/drm-intel: drm/i915/gen9: Add WaInPlaceDecompressionHang drm/i915/guc: Revert "drm/i915/guc: enable GuC loading & submission by default" drm/i915/bxt: Fix inadvertent CPU snooping due to incorrect MOCS config drm/i915/gen9: Clean up MOCS table definitions drm/i915: Set legacy properties when using legacy gamma set IOCTL. (v2) drm/i915: Enable polling when we don't have hpd drm/i915/vlv: Disable HPD in valleyview_crt_detect_hotplug() drm/i915/vlv: Reset the ADPA in vlv_display_power_well_init() drm/i915/vlv: Make intel_crt_reset() per-encoder drm/i915: Unbreak interrupts on pre-gen6 drm/i915/breadcrumbs: Queue hangcheck before sleeping
This commit is contained in:
commit
c3f8d8645e
13 changed files with 289 additions and 63 deletions
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@ -2413,6 +2413,9 @@ static int intel_runtime_suspend(struct device *device)
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assert_forcewakes_inactive(dev_priv);
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if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
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intel_hpd_poll_init(dev_priv);
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DRM_DEBUG_KMS("Device suspended\n");
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return 0;
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}
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@ -284,6 +284,9 @@ struct i915_hotplug {
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u32 short_port_mask;
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struct work_struct dig_port_work;
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struct work_struct poll_init_work;
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bool poll_enabled;
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/*
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* if we get a HPD irq from DP and a HPD irq from non-DP
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* the non-DP HPD could block the workqueue on a mode config
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@ -2743,6 +2746,8 @@ struct drm_i915_cmd_table {
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#define SKL_REVID_D0 0x3
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#define SKL_REVID_E0 0x4
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#define SKL_REVID_F0 0x5
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#define SKL_REVID_G0 0x6
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#define SKL_REVID_H0 0x7
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#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
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@ -2957,6 +2962,8 @@ void intel_hpd_init(struct drm_i915_private *dev_priv);
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void intel_hpd_init_work(struct drm_i915_private *dev_priv);
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void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
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bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
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bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
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void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
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/* i915_irq.c */
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static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
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@ -1501,15 +1501,6 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
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break;
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}
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/* Ensure that even if the GPU hangs, we get woken up.
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*
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* However, note that if no one is waiting, we never notice
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* a gpu hang. Eventually, we will have to wait for a resource
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* held by the GPU and so trigger a hangcheck. In the most
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* pathological case, this will be upon memory starvation!
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*/
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i915_queue_hangcheck(req->i915);
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timeout_remain = io_schedule_timeout(timeout_remain);
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if (timeout_remain == 0) {
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ret = -ETIME;
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@ -54,8 +54,8 @@ struct i915_params i915 __read_mostly = {
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.verbose_state_checks = 1,
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.nuclear_pageflip = 0,
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.edp_vswing = 0,
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.enable_guc_loading = -1,
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.enable_guc_submission = -1,
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.enable_guc_loading = 0,
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.enable_guc_submission = 0,
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.guc_log_level = -1,
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.enable_dp_mst = true,
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.inject_load_failure = 0,
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@ -203,12 +203,12 @@ MODULE_PARM_DESC(edp_vswing,
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module_param_named_unsafe(enable_guc_loading, i915.enable_guc_loading, int, 0400);
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MODULE_PARM_DESC(enable_guc_loading,
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"Enable GuC firmware loading "
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"(-1=auto [default], 0=never, 1=if available, 2=required)");
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"(-1=auto, 0=never [default], 1=if available, 2=required)");
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module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, int, 0400);
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MODULE_PARM_DESC(enable_guc_submission,
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"Enable GuC submission "
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"(-1=auto [default], 0=never, 1=if available, 2=required)");
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"(-1=auto, 0=never [default], 1=if available, 2=required)");
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module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
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MODULE_PARM_DESC(guc_log_level,
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@ -1686,6 +1686,9 @@ enum skl_disp_power_wells {
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#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
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#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
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#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
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#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
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#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
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@ -93,6 +93,15 @@ static void __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
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if (!b->irq_enabled ||
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test_bit(engine->id, &i915->gpu_error.missed_irq_rings))
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mod_timer(&b->fake_irq, jiffies + 1);
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/* Ensure that even if the GPU hangs, we get woken up.
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*
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* However, note that if no one is waiting, we never notice
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* a gpu hang. Eventually, we will have to wait for a resource
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* held by the GPU and so trigger a hangcheck. In the most
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* pathological case, this will be upon memory starvation!
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*/
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i915_queue_hangcheck(i915);
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}
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static void __intel_breadcrumbs_disable_irq(struct intel_breadcrumbs *b)
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@ -329,10 +329,25 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
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struct drm_device *dev = connector->dev;
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struct intel_crt *crt = intel_attached_crt(connector);
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struct drm_i915_private *dev_priv = to_i915(dev);
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bool reenable_hpd;
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u32 adpa;
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bool ret;
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u32 save_adpa;
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/*
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* Doing a force trigger causes a hpd interrupt to get sent, which can
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* get us stuck in a loop if we're polling:
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* - We enable power wells and reset the ADPA
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* - output_poll_exec does force probe on VGA, triggering a hpd
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* - HPD handler waits for poll to unlock dev->mode_config.mutex
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* - output_poll_exec shuts off the ADPA, unlocks
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* dev->mode_config.mutex
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* - HPD handler runs, resets ADPA and brings us back to the start
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*
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* Just disable HPD interrupts here to prevent this
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*/
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reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
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save_adpa = adpa = I915_READ(crt->adpa_reg);
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DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
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@ -357,6 +372,9 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
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DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
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if (reenable_hpd)
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intel_hpd_enable(dev_priv, crt->base.hpd_pin);
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return ret;
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}
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@ -717,11 +735,11 @@ static int intel_crt_set_property(struct drm_connector *connector,
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return 0;
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}
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static void intel_crt_reset(struct drm_connector *connector)
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void intel_crt_reset(struct drm_encoder *encoder)
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{
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struct drm_device *dev = connector->dev;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crt *crt = intel_attached_crt(connector);
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struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
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if (INTEL_INFO(dev)->gen >= 5) {
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u32 adpa;
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@ -743,7 +761,6 @@ static void intel_crt_reset(struct drm_connector *connector)
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*/
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static const struct drm_connector_funcs intel_crt_connector_funcs = {
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.reset = intel_crt_reset,
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.dpms = drm_atomic_helper_connector_dpms,
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.detect = intel_crt_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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@ -762,6 +779,7 @@ static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs
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};
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static const struct drm_encoder_funcs intel_crt_enc_funcs = {
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.reset = intel_crt_reset,
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.destroy = intel_encoder_destroy,
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};
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@ -904,5 +922,5 @@ void intel_crt_init(struct drm_device *dev)
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dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
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}
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intel_crt_reset(connector);
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intel_crt_reset(&crt->base.base);
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}
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@ -13924,8 +13924,50 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc)
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#undef for_each_intel_crtc_masked
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/*
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* FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
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* drm_atomic_helper_legacy_gamma_set() directly.
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*/
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static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
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u16 *red, u16 *green, u16 *blue,
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uint32_t size)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *config = &dev->mode_config;
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struct drm_crtc_state *state;
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int ret;
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ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
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if (ret)
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return ret;
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/*
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* Make sure we update the legacy properties so this works when
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* atomic is not enabled.
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*/
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state = crtc->state;
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drm_object_property_set_value(&crtc->base,
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config->degamma_lut_property,
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(state->degamma_lut) ?
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state->degamma_lut->base.id : 0);
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drm_object_property_set_value(&crtc->base,
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config->ctm_property,
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(state->ctm) ?
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state->ctm->base.id : 0);
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drm_object_property_set_value(&crtc->base,
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config->gamma_lut_property,
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(state->gamma_lut) ?
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state->gamma_lut->base.id : 0);
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return 0;
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}
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static const struct drm_crtc_funcs intel_crtc_funcs = {
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.gamma_set = drm_atomic_helper_legacy_gamma_set,
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.gamma_set = intel_atomic_legacy_gamma_set,
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.set_config = drm_atomic_helper_set_config,
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.set_property = drm_atomic_helper_crtc_set_property,
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.destroy = intel_crtc_destroy,
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@ -1102,7 +1102,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
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/* intel_crt.c */
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void intel_crt_init(struct drm_device *dev);
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void intel_crt_reset(struct drm_encoder *encoder);
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/* intel_ddi.c */
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void intel_ddi_clk_select(struct intel_encoder *encoder,
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@ -1425,6 +1425,8 @@ int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
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/* intel_dvo.c */
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void intel_dvo_init(struct drm_device *dev);
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/* intel_hotplug.c */
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void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
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/* legacy fbdev emulation in intel_fbdev.c */
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|
|
|
@ -452,31 +452,20 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
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*
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* This is a separate step from interrupt enabling to simplify the locking rules
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* in the driver load and resume code.
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*
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* Also see: intel_hpd_poll_init(), which enables connector polling
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*/
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void intel_hpd_init(struct drm_i915_private *dev_priv)
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{
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struct drm_device *dev = &dev_priv->drm;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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int i;
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for_each_hpd_pin(i) {
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dev_priv->hotplug.stats[i].count = 0;
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dev_priv->hotplug.stats[i].state = HPD_ENABLED;
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}
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list_for_each_entry(connector, &mode_config->connector_list, head) {
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struct intel_connector *intel_connector = to_intel_connector(connector);
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connector->polled = intel_connector->polled;
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|
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/* MST has a dynamic intel_connector->encoder and it's reprobing
|
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* is all handled by the MST helpers. */
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if (intel_connector->mst_port)
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continue;
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|
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if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
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intel_connector->encoder->hpd_pin > HPD_NONE)
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connector->polled = DRM_CONNECTOR_POLL_HPD;
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}
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WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
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schedule_work(&dev_priv->hotplug.poll_init_work);
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|
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/*
|
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* Interrupt setup is already guaranteed to be single-threaded, this is
|
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|
@ -488,10 +477,86 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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|
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void i915_hpd_poll_init_work(struct work_struct *work) {
|
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struct drm_i915_private *dev_priv =
|
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container_of(work, struct drm_i915_private,
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hotplug.poll_init_work);
|
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struct drm_device *dev = &dev_priv->drm;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
|
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bool enabled;
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mutex_lock(&dev->mode_config.mutex);
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enabled = READ_ONCE(dev_priv->hotplug.poll_enabled);
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|
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list_for_each_entry(connector, &mode_config->connector_list, head) {
|
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struct intel_connector *intel_connector =
|
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to_intel_connector(connector);
|
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connector->polled = intel_connector->polled;
|
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|
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/* MST has a dynamic intel_connector->encoder and it's reprobing
|
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* is all handled by the MST helpers. */
|
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if (intel_connector->mst_port)
|
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continue;
|
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|
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if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
|
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intel_connector->encoder->hpd_pin > HPD_NONE) {
|
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connector->polled = enabled ?
|
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DRM_CONNECTOR_POLL_CONNECT |
|
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DRM_CONNECTOR_POLL_DISCONNECT :
|
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DRM_CONNECTOR_POLL_HPD;
|
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}
|
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}
|
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|
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if (enabled)
|
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drm_kms_helper_poll_enable_locked(dev);
|
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|
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mutex_unlock(&dev->mode_config.mutex);
|
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|
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/*
|
||||
* We might have missed any hotplugs that happened while we were
|
||||
* in the middle of disabling polling
|
||||
*/
|
||||
if (!enabled)
|
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drm_helper_hpd_irq_event(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_hpd_poll_init - enables/disables polling for connectors with hpd
|
||||
* @dev_priv: i915 device instance
|
||||
* @enabled: Whether to enable or disable polling
|
||||
*
|
||||
* This function enables polling for all connectors, regardless of whether or
|
||||
* not they support hotplug detection. Under certain conditions HPD may not be
|
||||
* functional. On most Intel GPUs, this happens when we enter runtime suspend.
|
||||
* On Valleyview and Cherryview systems, this also happens when we shut off all
|
||||
* of the powerwells.
|
||||
*
|
||||
* Since this function can get called in contexts where we're already holding
|
||||
* dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
|
||||
* worker.
|
||||
*
|
||||
* Also see: intel_hpd_init(), which restores hpd handling.
|
||||
*/
|
||||
void intel_hpd_poll_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
|
||||
|
||||
/*
|
||||
* We might already be holding dev->mode_config.mutex, so do this in a
|
||||
* seperate worker
|
||||
* As well, there's no issue if we race here since we always reschedule
|
||||
* this worker anyway
|
||||
*/
|
||||
schedule_work(&dev_priv->hotplug.poll_init_work);
|
||||
}
|
||||
|
||||
void intel_hpd_init_work(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
INIT_WORK(&dev_priv->hotplug.hotplug_work, i915_hotplug_work_func);
|
||||
INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
|
||||
INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
|
||||
INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
|
||||
intel_hpd_irq_storm_reenable_work);
|
||||
}
|
||||
|
@ -508,5 +573,33 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
|
|||
|
||||
cancel_work_sync(&dev_priv->hotplug.dig_port_work);
|
||||
cancel_work_sync(&dev_priv->hotplug.hotplug_work);
|
||||
cancel_work_sync(&dev_priv->hotplug.poll_init_work);
|
||||
cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
|
||||
}
|
||||
|
||||
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
|
||||
{
|
||||
bool ret = false;
|
||||
|
||||
if (pin == HPD_NONE)
|
||||
return false;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
|
||||
dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
|
||||
ret = true;
|
||||
}
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
|
||||
{
|
||||
if (pin == HPD_NONE)
|
||||
return;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
}
|
||||
|
|
|
@ -66,9 +66,10 @@ struct drm_i915_mocs_table {
|
|||
#define L3_WB 3
|
||||
|
||||
/* Target cache */
|
||||
#define ELLC 0
|
||||
#define LLC 1
|
||||
#define LLC_ELLC 2
|
||||
#define LE_TC_PAGETABLE 0
|
||||
#define LE_TC_LLC 1
|
||||
#define LE_TC_LLC_ELLC 2
|
||||
#define LE_TC_LLC_ELLC_ALT 3
|
||||
|
||||
/*
|
||||
* MOCS tables
|
||||
|
@ -96,34 +97,67 @@ struct drm_i915_mocs_table {
|
|||
* end.
|
||||
*/
|
||||
static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
|
||||
/* { 0x00000009, 0x0010 } */
|
||||
{ (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
|
||||
LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
|
||||
(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
|
||||
/* { 0x00000038, 0x0030 } */
|
||||
{ (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
|
||||
LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
|
||||
(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
|
||||
/* { 0x0000003b, 0x0030 } */
|
||||
{ (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
|
||||
LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
|
||||
(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
|
||||
{ /* 0x00000009 */
|
||||
.control_value = LE_CACHEABILITY(LE_UC) |
|
||||
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
|
||||
LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
|
||||
LE_PFM(0) | LE_SCF(0),
|
||||
|
||||
/* 0x0010 */
|
||||
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
|
||||
},
|
||||
{
|
||||
/* 0x00000038 */
|
||||
.control_value = LE_CACHEABILITY(LE_PAGETABLE) |
|
||||
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
|
||||
LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
|
||||
LE_PFM(0) | LE_SCF(0),
|
||||
/* 0x0030 */
|
||||
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
|
||||
},
|
||||
{
|
||||
/* 0x0000003b */
|
||||
.control_value = LE_CACHEABILITY(LE_WB) |
|
||||
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
|
||||
LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
|
||||
LE_PFM(0) | LE_SCF(0),
|
||||
/* 0x0030 */
|
||||
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
|
||||
},
|
||||
};
|
||||
|
||||
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
|
||||
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
|
||||
/* { 0x00000009, 0x0010 } */
|
||||
{ (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
|
||||
LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
|
||||
(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
|
||||
/* { 0x00000038, 0x0030 } */
|
||||
{ (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
|
||||
LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
|
||||
(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
|
||||
/* { 0x0000003b, 0x0030 } */
|
||||
{ (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
|
||||
LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
|
||||
(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
|
||||
{
|
||||
/* 0x00000009 */
|
||||
.control_value = LE_CACHEABILITY(LE_UC) |
|
||||
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
|
||||
LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
|
||||
LE_PFM(0) | LE_SCF(0),
|
||||
|
||||
/* 0x0010 */
|
||||
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
|
||||
},
|
||||
{
|
||||
/* 0x00000038 */
|
||||
.control_value = LE_CACHEABILITY(LE_PAGETABLE) |
|
||||
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
|
||||
LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
|
||||
LE_PFM(0) | LE_SCF(0),
|
||||
|
||||
/* 0x0030 */
|
||||
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
|
||||
},
|
||||
{
|
||||
/* 0x00000039 */
|
||||
.control_value = LE_CACHEABILITY(LE_UC) |
|
||||
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
|
||||
LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
|
||||
LE_PFM(0) | LE_SCF(0),
|
||||
|
||||
/* 0x0030 */
|
||||
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -1109,6 +1109,11 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
|
|||
/* WaDisableGafsUnitClkGating:skl */
|
||||
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
|
||||
|
||||
/* WaInPlaceDecompressionHang:skl */
|
||||
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
|
||||
WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
|
||||
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
|
||||
|
||||
/* WaDisableLSQCROPERFforOCL:skl */
|
||||
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
||||
if (ret)
|
||||
|
@ -1178,6 +1183,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
|
|||
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
||||
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
||||
|
||||
/* WaInPlaceDecompressionHang:bxt */
|
||||
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
|
||||
WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
|
||||
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -1225,6 +1235,10 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
|
|||
GEN7_HALF_SLICE_CHICKEN1,
|
||||
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
||||
|
||||
/* WaInPlaceDecompressionHang:kbl */
|
||||
WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
|
||||
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
|
||||
|
||||
/* WaDisableLSQCROPERFforOCL:kbl */
|
||||
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
||||
if (ret)
|
||||
|
@ -1305,7 +1319,8 @@ static int init_render_ring(struct intel_engine_cs *engine)
|
|||
if (IS_GEN(dev_priv, 6, 7))
|
||||
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
|
||||
|
||||
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
|
||||
if (INTEL_INFO(dev_priv)->gen >= 6)
|
||||
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
|
||||
|
||||
return init_workarounds_ring(engine);
|
||||
}
|
||||
|
|
|
@ -1078,6 +1078,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
|
|||
|
||||
static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_encoder *encoder;
|
||||
enum pipe pipe;
|
||||
|
||||
/*
|
||||
|
@ -1113,6 +1114,12 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
|
|||
|
||||
intel_hpd_init(dev_priv);
|
||||
|
||||
/* Re-enable the ADPA, if we have one */
|
||||
for_each_intel_encoder(&dev_priv->drm, encoder) {
|
||||
if (encoder->type == INTEL_OUTPUT_ANALOG)
|
||||
intel_crt_reset(&encoder->base);
|
||||
}
|
||||
|
||||
i915_redisable_vga_power_on(&dev_priv->drm);
|
||||
}
|
||||
|
||||
|
@ -1126,6 +1133,8 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
|
|||
synchronize_irq(dev_priv->drm.irq);
|
||||
|
||||
intel_power_sequencer_reset(dev_priv);
|
||||
|
||||
intel_hpd_poll_init(dev_priv);
|
||||
}
|
||||
|
||||
static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
|
||||
|
|
Loading…
Reference in a new issue