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Powerdomain drivers for rv1126 and rk3588 socs, keep current state of

Browse source 
power-domains instead of always enabling when adding them, add rv1126
 io domains and add binding for another "general register files" syscon.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmMb4uEQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgZ3iB/4wlzvfB7fEZFjydhKp3hgXn/1Q1fkGZWtP
 JHhQC5NS1jd1IRTFr4PNx5Imp9He0CqCnNbgXf9D/3lbJbK5q2GydZ+ir68fJ3KS
 lu8kMrbeR3FAWq2PWHswDz+ttziKNjLb7x6o30+oBfGAhMq9bRrg9f65Q9dNCHEe
 xQy4lXP+LYHlYZRYN1k9MYD5oetYmFQAmCamR1dwzX/QiyI/zj36/IaVk5LT/Ywn
 nyF6HR+6pESMSuTpBgLEWPoolMS9LWu4iYXU3j3py8AwZzq4ukC9v8uH28DOlVa7
 FPAAk/33eRqnzX7oTnvyGzJH0FYMA60BkHtW5jDaQPSCcuaMGYiT
 =aXMw
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfS4YACgkQmmx57+YA
 GNk8zQ//f7xINfYva0Ptx2tHORVn/ei5t5yZ4enroZO+8LdDX6AyDAu03PAvfEAn
 DughmkIyCwQVZWjKJCAqh5j4PP8IVDRFHw2PZtjNuTXMrXUB4X9AsQXzY5anayr/
 E8ebMoYSZAujlVhzl+0Eoq0OkXkF5OKmYLoXD4X1CrDjbEDYmkl3OUR+e39JGYH7
 NWyh+pnR+z9zi00GGyy79n/I8hDmy+8STJrySw9oZxFyq6IFbelVuMPrbUK5PUZb
 v1Xb3cRpybraO7IGhYzkSTbbZbGqz6pUAea0JeAtdrAqNGM9JDeCXF0x5hfth/9l
 RpU+P2NPAV2D3LO0rcwJSDoraJ1TSg26M/Ou+zM2GgR+y6uRKSdkDk3dx4FlBx4G
 XrAsAgBV8ak5AvWsD4W1WXHHu7EqdMHBoTwZVlVUT79IJlZM0EvXtTtgiI5HM7Gl
 5F/Ybl1FdmDzP1L11UCKCnxBYgTDaiHwT598s8G4bKlmsKBYo/yP1jKwA4weVOdv
 W36yPe3DqK9xkt/zkpJHf+mW9aj7Ib3Bp2ET/K8Rky0BFHjFSKHz/nutkHpxmibD
 psUFyrBuHx/Owqj0F1HXsXPpvZDrlkwdphVN9YA2yZM1h52IEkUyVJvjfJhlN0E1
 kuLfxJycqTNJJlHYTgUaZR0lphwZYafiOnmgIqfqxTmIR8dPZL4=
 =niMz
 -----END PGP SIGNATURE-----

Merge tag 'v6.1-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers

Powerdomain drivers for rv1126 and rk3588 socs, keep current state of
power-domains instead of always enabling when adding them, add rv1126
io domains and add binding for another "general register files" syscon.

* tag 'v6.1-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: power-domain: add power domain support for rk3588
  soc: rockchip: power-domain: do not enable domain when adding it
  dt-bindings: power: rockchip: Add bindings for rk3588
  dt-bindings: arm: rockchip: add rk5388 compatible string to pmu.yaml
  dt-bindings: power: add power-domain header for rk3588
  soc: rockchip: io-domain: Add RV1126 IO domains
  dt-bindings: power: rockchip: Document RV1126 PMU IO domains
  soc: rockchip: power-domain: Add RV1126 power domains
  dt-bindings: power: rockchip: Document RV1126 power-controller
  dt-bindings: power: Add power-domain header for RV1126
  dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf

Link: https://lore.kernel.org/r/2252399.ElGaqSPkdT@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-09-12 17:08:53 +02:00
commit c3fe295c2e
8 changed files with 280 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
View file

@ -25,6 +25,7 @@ select:
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3588-pmu
required:
- compatible
@ -39,6 +40,7 @@ properties:
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3588-pmu
- const: syscon
- const: simple-mfd

4
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
View file

@ -41,6 +41,8 @@ properties:
- rockchip,rk3368-power-controller
- rockchip,rk3399-power-controller
- rockchip,rk3568-power-controller
- rockchip,rk3588-power-controller
- rockchip,rv1126-power-controller
"#power-domain-cells":
const: 1
@ -119,6 +121,8 @@ $defs:
"include/dt-bindings/power/rk3368-power.h"
"include/dt-bindings/power/rk3399-power.h"
"include/dt-bindings/power/rk3568-power.h"
"include/dt-bindings/power/rk3588-power.h"
"include/dt-bindings/power/rockchip,rv1126-power.h"
clocks:
minItems: 1

30
Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
View file

@ -58,6 +58,7 @@ properties:
- rockchip,rk3568-pmu-io-voltage-domain
- rockchip,rv1108-io-voltage-domain
- rockchip,rv1108-pmu-io-voltage-domain
- rockchip,rv1126-pmu-io-voltage-domain
required:
- compatible
@ -78,6 +79,7 @@ allOf:
- $ref: "#/$defs/rk3568-pmu"
- $ref: "#/$defs/rv1108"
- $ref: "#/$defs/rv1108-pmu"
- $ref: "#/$defs/rv1126-pmu"
$defs:
px30:
@ -344,6 +346,34 @@ $defs:
pmu-supply:
description: The supply connected to PMUIO_VDD.
rv1126-pmu:
if:
properties:
compatible:
contains:
const: rockchip,rv1126-pmu-io-voltage-domain
then:
properties:
vccio1-supply:
description: The supply connected to VCCIO1.
vccio2-supply:
description: The supply connected to VCCIO2.
vccio3-supply:
description: The supply connected to VCCIO3.
vccio4-supply:
description: The supply connected to VCCIO4.
vccio5-supply:
description: The supply connected to VCCIO5.
vccio6-supply:
description: The supply connected to VCCIO6.
vccio7-supply:
description: The supply connected to VCCIO7.
pmuio0-supply:
description: The supply connected to PMUIO0.
pmuio1-supply:
description: The supply connected to PMUIO1.
examples:
- |
io-domains {

3
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View file

@ -16,9 +16,12 @@ properties:
- enum:
- rockchip,rk3288-sgrf
- rockchip,rk3566-pipe-grf
- rockchip,rk3568-pcie3-phy-grf
- rockchip,rk3568-pipe-grf
- rockchip,rk3568-pipe-phy-grf
- rockchip,rk3568-usb2phy-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
- rockchip,rv1108-usbgrf
- const: syscon
- items:

20
drivers/soc/rockchip/io-domain.c
View file

@ -491,6 +491,22 @@ static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
},
};
static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = {
.grf_offset = 0x140,
.supply_names = {
NULL,
"vccio1",
"vccio2",
"vccio3",
"vccio4",
"vccio5",
"vccio6",
"vccio7",
"pmuio0",
"pmuio1",
},
};
static const struct of_device_id rockchip_iodomain_match[] = {
{
.compatible = "rockchip,px30-io-voltage-domain",
@ -544,6 +560,10 @@ static const struct of_device_id rockchip_iodomain_match[] = {
.compatible = "rockchip,rv1108-pmu-io-voltage-domain",
.data = &soc_data_rv1108_pmu
},
{
.compatible = "rockchip,rv1126-pmu-io-voltage-domain",
.data = &soc_data_rv1126_pmu
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);

130
drivers/soc/rockchip/pm_domains.c
View file

@ -19,6 +19,7 @@
#include <linux/mfd/syscon.h>
#include <soc/rockchip/pm_domains.h>
#include <dt-bindings/power/px30-power.h>
#include <dt-bindings/power/rockchip,rv1126-power.h>
#include <dt-bindings/power/rk3036-power.h>
#include <dt-bindings/power/rk3066-power.h>
#include <dt-bindings/power/rk3128-power.h>
@ -30,6 +31,7 @@
#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/power/rk3399-power.h>
#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/power/rk3588-power.h>
struct rockchip_domain_info {
const char *name;
@ -41,6 +43,9 @@ struct rockchip_domain_info {
bool active_wakeup;
int pwr_w_mask;
int req_w_mask;
int repair_status_mask;
u32 pwr_offset;
u32 req_offset;
};
struct rockchip_pmu_info {
@ -49,6 +54,7 @@ struct rockchip_pmu_info {
u32 req_offset;
u32 idle_offset;
u32 ack_offset;
u32 repair_status_offset;
u32 core_pwrcnt_offset;
u32 gpu_pwrcnt_offset;
@ -113,6 +119,22 @@ struct rockchip_pmu {
.active_wakeup = wakeup, \
}
#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
.req_mask = (req), \
.idle_mask = (idle), \
.ack_mask = (ack), \
.active_wakeup = wakeup, \
}
#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
{ \
.name = _name, \
@ -126,6 +148,9 @@ struct rockchip_pmu {
#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
#define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
@ -244,6 +269,9 @@ void rockchip_pmu_unblock(void)
}
EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
@ -268,6 +296,7 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
const struct rockchip_domain_info *pd_info = pd->info;
struct generic_pm_domain *genpd = &pd->genpd;
struct rockchip_pmu *pmu = pd->pmu;
u32 pd_req_offset = pd_info->req_offset;
unsigned int target_ack;
unsigned int val;
bool is_idle;
@ -276,11 +305,11 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
if (pd_info->req_mask == 0)
return 0;
else if (pd_info->req_w_mask)
regmap_write(pmu->regmap, pmu->info->req_offset,
regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
idle ? (pd_info->req_mask | pd_info->req_w_mask) :
pd_info->req_w_mask);
else
regmap_update_bits(pmu->regmap, pmu->info->req_offset,
regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
pd_info->req_mask, idle ? -1U : 0);
wmb();
@ -363,6 +392,12 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
struct rockchip_pmu *pmu = pd->pmu;
unsigned int val;
if (pd->info->repair_status_mask) {
regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
/* 1'b1: power on, 1'b0: power off */
return val & pd->info->repair_status_mask;
}
/* check idle status for idle-only domains */
if (pd->info->status_mask == 0)
return !rockchip_pmu_domain_is_idle(pd);
@ -378,16 +413,17 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
u32 pd_pwr_offset = pd->info->pwr_offset;
bool is_on;
if (pd->info->pwr_mask == 0)
return;
else if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset,
regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask));
else
regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
pd->info->pwr_mask, on ? 0 : -1U);
wmb();
@ -514,6 +550,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
node, id);
return -EINVAL;
}
/* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
if (pmu->genpd_data.domains[id])
return 0;
pd_info = &pmu->info->domain_info[id];
if (!pd_info) {
@ -595,14 +634,6 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
}
}
error = rockchip_pd_power(pd, true);
if (error) {
dev_err(pmu->dev,
"failed to power on domain '%pOFn': %d\n",
node, error);
goto err_unprepare_clocks;
}
if (pd->info->name)
pd->genpd.name = pd->info->name;
else
@ -614,7 +645,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
pd->genpd.flags = GENPD_FLAG_PM_CLK;
if (pd_info->active_wakeup)
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
pm_genpd_init(&pd->genpd, NULL, false);
pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
pmu->genpd_data.domains[id] = &pd->genpd;
return 0;
@ -855,6 +886,16 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
};
static const struct rockchip_domain_info rv1126_pm_domains[] = {
[RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
[RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
[RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
[RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
[RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
[RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
[RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
};
static const struct rockchip_domain_info rk3036_pm_domains[] = {
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
@ -982,6 +1023,38 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
[RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
[RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
[RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
[RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
[RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
[RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
[RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
[RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
[RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
[RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
[RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
[RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
[RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
[RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
[RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
[RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
[RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
[RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
[RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
[RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
[RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
[RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
[RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
[RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
[RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
[RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
[RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
[RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
[RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
};
static const struct rockchip_pmu_info px30_pmu = {
.pwr_offset = 0x18,
.status_offset = 0x20,
@ -1128,6 +1201,29 @@ static const struct rockchip_pmu_info rk3568_pmu = {
.domain_info = rk3568_pm_domains,
};
static const struct rockchip_pmu_info rk3588_pmu = {
.pwr_offset = 0x14c,
.status_offset = 0x180,
.req_offset = 0x10c,
.idle_offset = 0x120,
.ack_offset = 0x118,
.repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
.domain_info = rk3588_pm_domains,
};
static const struct rockchip_pmu_info rv1126_pmu = {
.pwr_offset = 0x110,
.status_offset = 0x108,
.req_offset = 0xc0,
.idle_offset = 0xd8,
.ack_offset = 0xd0,
.num_domains = ARRAY_SIZE(rv1126_pm_domains),
.domain_info = rv1126_pm_domains,
};
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@ -1177,6 +1273,14 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3568-power-controller",
.data = (void *)&rk3568_pmu,
},
{
.compatible = "rockchip,rk3588-power-controller",
.data = (void *)&rk3588_pmu,
},
{
.compatible = "rockchip,rv1126-power-controller",
.data = (void *)&rv1126_pmu,
},
{ /* sentinel */ },
};

69
include/dt-bindings/power/rk3588-power.h Normal file
View file

@ -0,0 +1,69 @@
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__
#define __DT_BINDINGS_POWER_RK3588_POWER_H__
/* VD_LITDSU */
#define RK3588_PD_CPU_0 0
#define RK3588_PD_CPU_1 1
#define RK3588_PD_CPU_2 2
#define RK3588_PD_CPU_3 3
/* VD_BIGCORE0 */
#define RK3588_PD_CPU_4 4
#define RK3588_PD_CPU_5 5
/* VD_BIGCORE1 */
#define RK3588_PD_CPU_6 6
#define RK3588_PD_CPU_7 7
/* VD_NPU */
#define RK3588_PD_NPU 8
#define RK3588_PD_NPUTOP 9
#define RK3588_PD_NPU1 10
#define RK3588_PD_NPU2 11
/* VD_GPU */
#define RK3588_PD_GPU 12
/* VD_VCODEC */
#define RK3588_PD_VCODEC 13
#define RK3588_PD_RKVDEC0 14
#define RK3588_PD_RKVDEC1 15
#define RK3588_PD_VENC0 16
#define RK3588_PD_VENC1 17
/* VD_DD01 */
#define RK3588_PD_DDR01 18
/* VD_DD23 */
#define RK3588_PD_DDR23 19
/* VD_LOGIC */
#define RK3588_PD_CENTER 20
#define RK3588_PD_VDPU 21
#define RK3588_PD_RGA30 22
#define RK3588_PD_AV1 23
#define RK3588_PD_VOP 24
#define RK3588_PD_VO0 25
#define RK3588_PD_VO1 26
#define RK3588_PD_VI 27
#define RK3588_PD_ISP1 28
#define RK3588_PD_FEC 29
#define RK3588_PD_RGA31 30
#define RK3588_PD_USB 31
#define RK3588_PD_PHP 32
#define RK3588_PD_GMAC 33
#define RK3588_PD_PCIE 34
#define RK3588_PD_NVM 35
#define RK3588_PD_NVM0 36
#define RK3588_PD_SDIO 37
#define RK3588_PD_AUDIO 38
#define RK3588_PD_SECURE 39
#define RK3588_PD_SDMMC 40
#define RK3588_PD_CRYPTO 41
#define RK3588_PD_BUS 42
/* VD_PMU */
#define RK3588_PD_PMU1 43
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
#define __DT_BINDINGS_POWER_RV1126_POWER_H__
/* VD_CORE */
#define RV1126_PD_CPU_0 0
#define RV1126_PD_CPU_1 1
#define RV1126_PD_CPU_2 2
#define RV1126_PD_CPU_3 3
#define RV1126_PD_CORE_ALIVE 4
/* VD_PMU */
#define RV1126_PD_PMU 5
#define RV1126_PD_PMU_ALIVE 6
/* VD_NPU */
#define RV1126_PD_NPU 7
/* VD_VEPU */
#define RV1126_PD_VEPU 8
/* VD_LOGIC */
#define RV1126_PD_VI 9
#define RV1126_PD_VO 10
#define RV1126_PD_ISPP 11
#define RV1126_PD_VDPU 12
#define RV1126_PD_CRYPTO 13
#define RV1126_PD_DDR 14
#define RV1126_PD_NVM 15
#define RV1126_PD_SDIO 16
#define RV1126_PD_USB 17
#define RV1126_PD_LOGIC_ALIVE 18
#endif