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arm64: dts: imx8dxl: add lpspi support
Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem. Change irq number for 8dxl. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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2 changed files with 128 additions and 0 deletions
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@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg {
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clock-output-names = "dma_ipg_clk";
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};
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lpspi0: spi@5a000000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x5a000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&spi0_lpcg 0>,
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<&spi0_lpcg 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <20000000>;
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power-domains = <&pd IMX_SC_R_SPI_0>;
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status = "disabled";
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};
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lpspi1: spi@5a010000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x5a010000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&spi1_lpcg 0>,
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<&spi1_lpcg 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <60000000>;
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power-domains = <&pd IMX_SC_R_SPI_1>;
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status = "disabled";
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};
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lpspi2: spi@5a020000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x5a020000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&spi2_lpcg 0>,
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<&spi2_lpcg 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <60000000>;
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power-domains = <&pd IMX_SC_R_SPI_2>;
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status = "disabled";
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};
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lpspi3: spi@5a030000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x5a030000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&spi3_lpcg 0>,
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<&spi3_lpcg 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <60000000>;
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power-domains = <&pd IMX_SC_R_SPI_3>;
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status = "disabled";
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};
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lpuart0: serial@5a060000 {
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reg = <0x5a060000 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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@ -60,6 +124,54 @@ lpuart3: serial@5a090000 {
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status = "disabled";
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};
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spi0_lpcg: clock-controller@5a400000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a400000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "spi0_lpcg_clk",
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"spi0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_SPI_0>;
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};
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spi1_lpcg: clock-controller@5a410000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a410000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "spi1_lpcg_clk",
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"spi1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_SPI_1>;
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};
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spi2_lpcg: clock-controller@5a420000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a420000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "spi2_lpcg_clk",
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"spi2_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_SPI_2>;
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};
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spi3_lpcg: clock-controller@5a430000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a430000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
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<&dma_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "spi3_lpcg_clk",
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"spi3_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_SPI_3>;
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};
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uart0_lpcg: clock-controller@5a460000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5a460000 0x10000>;
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@ -54,3 +54,19 @@ &lpuart3 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpspi0 {
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpspi1 {
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpspi2 {
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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};
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&lpspi3 {
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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};
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