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Pin control fixes for the v4.10 series:
- One fix to the AMD pinctrl ACPI glue. - Fix requests on the Meson driver. - Fix bitfield widths on Samsungs Exynos 5433. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJYbmeqAAoJEEEQszewGV1zVHoP/2jqDEtyad3eUUG+LjRof8m8 opHd7WuG+V7ZqPHgWJdDAUTtO8Q9aYIZEQpdunIsp+xwuW8Moyv6a3RaGb5AA5Jr goYTuoJt+SVGLZPPHlb1rIQoXRkh433LWz4f7hyVNASU/UDTQ4R1XUhnpyewRJLL P9gHZr5tJjxsTj/Y8u6md6TIBk4gjQWVChePusw4U5wioo9xbJPFl0rY+jywFoII cunKU9VxQbxD8nRX+uQMWStqtjh7NSAFTsm/WimtkgKC+6ZXSJmiKHAkDITfBCfQ VmDG4NqyFoTfMZ/QtVgJ3zSyjQ3hjZwzyVf82RBcYh8INIvDg+9RZvIpSuHNx4EK 6K82pRDpUC7xCyBBVGAz+dTth1FAXRIng/EcWfIcFLyGqR8Xv1T7tVHCX4Zg148s EVLFbJ9wTAW76jic2/n8CC9M4sJrBnUeSEG5gHnbr+ms+KtAnoJrZEnAx84lIwFD SdhZLTIwr5eIpw+In0XTwUl9Nd9m7tx0etGPq9PdhHdtpSHeqWL+LNZw8i7hFcvj 5GpsM+Q3U7wf2UQQzLGv1Dm9vsFyW9qDEJqldDCc20dDI0RXN9sydJz3I44wmEfs yUxuNjxCXqqsyNCHbYO3loZJG2ua1SYsAMVQdYe9k4gDnwAqVfesd6quYI19UEKw u3fYMTUChP+MWEXbFZqg =t6nv -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "Three small pin control fixes for the v4.10 series. Very little to say about them, just driver fixes. - one fix to the AMD pinctrl ACPI glue - fix requests on the Meson driver - fix bitfield widths on Samsungs Exynos 5433" * tag 'pinctrl-v4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433 pinctrl: meson: fix gpio request disabling other modes pinctrl/amd: Set the level based on ACPI tables
This commit is contained in:
commit
c433eb70f3
4 changed files with 90 additions and 53 deletions
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@ -212,7 +212,7 @@ static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
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meson_pmx_disable_other_groups(pc, offset, -1);
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return 0;
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}
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@ -382,26 +382,21 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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int ret = 0;
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u32 pin_reg;
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unsigned long flags;
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bool level_trig;
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u32 active_level;
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unsigned long flags, irq_flags;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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/*
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* When level_trig is set EDGE and active_level is set HIGH in BIOS
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* default settings, ignore incoming settings from client and use
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* BIOS settings to configure GPIO register.
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/* Ignore the settings coming from the client and
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* read the values from the ACPI tables
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* while setting the trigger type
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*/
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level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
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active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
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if(level_trig &&
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((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))
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type = IRQ_TYPE_EDGE_FALLING;
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irq_flags = irq_get_trigger_type(d->irq);
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if (irq_flags != IRQ_TYPE_NONE)
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type = irq_flags;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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@ -56,6 +56,17 @@ static const struct samsung_pin_bank_type bank_type_alive = {
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
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static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
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.fld_width = { 4, 1, 2, 4, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
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};
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static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
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.fld_width = { 4, 1, 2, 4, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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static void exynos_irq_mask(struct irq_data *irqd)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(irqd);
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@ -1335,82 +1346,82 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
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/* pin banks of exynos5433 pin-controller - ALIVE */
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static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
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EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
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EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
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EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
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EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
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EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
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EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
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EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
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EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
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EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
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EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
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EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
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EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
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EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
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EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
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EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
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};
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/* pin banks of exynos5433 pin-controller - AUD */
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static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
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EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
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EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
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EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
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};
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/* pin banks of exynos5433 pin-controller - CPIF */
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static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
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EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
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};
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/* pin banks of exynos5433 pin-controller - eSE */
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static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
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EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
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};
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/* pin banks of exynos5433 pin-controller - FINGER */
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static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
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EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
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};
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/* pin banks of exynos5433 pin-controller - FSYS */
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static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
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EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
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EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
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EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
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EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
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EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
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EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
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EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
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EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
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EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
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};
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/* pin banks of exynos5433 pin-controller - IMEM */
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static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
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};
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/* pin banks of exynos5433 pin-controller - NFC */
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static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
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EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
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};
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/* pin banks of exynos5433 pin-controller - PERIC */
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static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
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EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
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EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
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EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
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EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
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EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
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EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
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EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
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EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
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EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
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EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
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EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
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EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
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EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
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EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
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EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
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EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
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EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
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EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
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EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
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EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
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EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
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EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
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EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
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EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
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EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
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EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
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EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
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EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
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EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
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};
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/* pin banks of exynos5433 pin-controller - TOUCH */
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static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
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EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
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EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
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};
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/*
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@ -90,6 +90,37 @@
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.pctl_res_idx = pctl_idx, \
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} \
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#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &exynos5433_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &exynos5433_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
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{ \
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.type = &exynos5433_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id, \
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.pctl_res_idx = pctl_idx, \
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} \
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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