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arm: Xilinx Zynq cleanup patches for v3.12
This branch contains these fixes: - SLCR cleanup - Hotplug cleanup -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlITAu0ACgkQykllyylKDCEaRQCfSvHsoH+Pnucmj07bT63vCPLZ /iMAnRmVpjr2BR0nEoC2aFYGs2nprn/A =ueLK -----END PGP SIGNATURE----- Merge tag 'zynq-cleanup-for-3.12' of git://git.xilinx.com/linux-xlnx into next/cleanup From: Michal Simek: arm: Xilinx Zynq cleanup patches for v3.12 This branch contains these fixes: - SLCR cleanup - Hotplug cleanup * tag 'zynq-cleanup-for-3.12' of git://git.xilinx.com/linux-xlnx: arm: zynq: hotplug: Remove unreachable code arm: zynq: slcr: Use read-modify-write for register writes arm: zynq: slcr: Clean up #defines arm: zynq: slcr: Remove redundant header #includes Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
commit
c454194612
2 changed files with 22 additions and 78 deletions
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@ -40,44 +40,6 @@ static inline void zynq_cpu_enter_lowpower(void)
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: "cc");
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: "cc");
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}
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}
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static inline void zynq_cpu_leave_lowpower(void)
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{
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unsigned int v;
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asm volatile(
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" mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, #0x40\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (CR_C)
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: "cc");
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}
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static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
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{
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/*
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* there is no power-control hardware on this platform, so all
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* we can do is put the core into WFI; this is safe as the calling
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* code will have already disabled interrupts
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*/
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for (;;) {
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dsb();
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wfi();
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/*
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* Getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* Just note it happening - when we're woken, we can report
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* its occurrence.
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*/
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(*spurious)++;
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}
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}
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/*
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/*
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* platform-specific code to shutdown a CPU
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* platform-specific code to shutdown a CPU
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*
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*
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@ -85,20 +47,13 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
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*/
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*/
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void zynq_platform_cpu_die(unsigned int cpu)
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void zynq_platform_cpu_die(unsigned int cpu)
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{
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{
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int spurious = 0;
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/*
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* we're ready for shutdown now, so do it
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*/
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zynq_cpu_enter_lowpower();
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zynq_cpu_enter_lowpower();
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zynq_platform_do_lowpower(cpu, &spurious);
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/*
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/*
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* bring this CPU back into the world of cache
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* there is no power-control hardware on this platform, so all
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* coherency, and then restore interrupts
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* we can do is put the core into WFI; this is safe as the calling
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* code will have already disabled interrupts
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*/
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*/
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zynq_cpu_leave_lowpower();
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for (;;)
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cpu_do_idle();
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if (spurious)
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pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
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}
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}
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@ -14,32 +14,21 @@
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* 02139, USA.
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* 02139, USA.
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*/
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*/
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/fs.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <linux/uaccess.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/clk/zynq.h>
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#include <linux/clk/zynq.h>
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#include "common.h"
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#include "common.h"
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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/* register offsets */
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#define SLCR_UNLOCK 0x8 /* SCLR unlock register */
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#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
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#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
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#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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#define SLCR_A9_CPU_RST 0x1
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#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */
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#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */
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void __iomem *zynq_slcr_base;
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void __iomem *zynq_slcr_base;
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/**
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/**
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@ -54,15 +43,15 @@ void zynq_slcr_system_reset(void)
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* Note that this seems to require raw i/o
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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* functions or there's a lockup?
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*/
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*/
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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/*
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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* This is a temporary solution until we know more.
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*/
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*/
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reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
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reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
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writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
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writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
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}
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}
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@ -72,11 +61,11 @@ void zynq_slcr_system_reset(void)
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*/
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*/
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void zynq_slcr_cpu_start(int cpu)
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void zynq_slcr_cpu_start(int cpu)
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{
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{
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/* enable CPUn */
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel(SLCR_A9_CPU_CLKSTOP << cpu,
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reg &= ~(SLCR_A9_CPU_RST << cpu);
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zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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/* enable CLK for CPUn */
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reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
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writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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}
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/**
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/**
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@ -85,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
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*/
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*/
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void zynq_slcr_cpu_stop(int cpu)
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void zynq_slcr_cpu_stop(int cpu)
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{
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{
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/* stop CLK and reset CPUn */
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
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reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
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zynq_slcr_base + SLCR_A9_CPU_RST_CTRL);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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}
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/**
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/**
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@ -113,7 +102,7 @@ int __init zynq_slcr_init(void)
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}
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}
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/* unlock the SLCR so that registers can be changed */
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/* unlock the SLCR so that registers can be changed */
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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