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powerpc/ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR
This patch enables support for all three TM checkpointed SPR states related ELF core note NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR based ptrace requests through PTRACE_GETREGSET, PTRACE_SETREGSET calls. This is achieved through adding three new register sets REGSET_TM_CTAR, REGSET_TM_CPPR and REGSET_TM_CDSCR in powerpc corresponding to the ELF core note sections added. It implements the get, set and active functions for all these new register sets added. Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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08e1c01d6a
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1 changed files with 178 additions and 0 deletions
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@ -1542,6 +1542,151 @@ static int tm_spr_set(struct task_struct *target,
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2 * sizeof(u64), 3 * sizeof(u64));
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return ret;
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}
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static int tm_tar_active(struct task_struct *target,
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const struct user_regset *regset)
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{
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (MSR_TM_ACTIVE(target->thread.regs->msr))
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return regset->n;
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return 0;
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}
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static int tm_tar_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (!MSR_TM_ACTIVE(target->thread.regs->msr))
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return -ENODATA;
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.tm_tar, 0, sizeof(u64));
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return ret;
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}
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static int tm_tar_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (!MSR_TM_ACTIVE(target->thread.regs->msr))
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return -ENODATA;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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&target->thread.tm_tar, 0, sizeof(u64));
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return ret;
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}
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static int tm_ppr_active(struct task_struct *target,
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const struct user_regset *regset)
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{
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (MSR_TM_ACTIVE(target->thread.regs->msr))
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return regset->n;
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return 0;
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}
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static int tm_ppr_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (!MSR_TM_ACTIVE(target->thread.regs->msr))
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return -ENODATA;
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.tm_ppr, 0, sizeof(u64));
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return ret;
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}
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static int tm_ppr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (!MSR_TM_ACTIVE(target->thread.regs->msr))
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return -ENODATA;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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&target->thread.tm_ppr, 0, sizeof(u64));
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return ret;
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}
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static int tm_dscr_active(struct task_struct *target,
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const struct user_regset *regset)
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{
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (MSR_TM_ACTIVE(target->thread.regs->msr))
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return regset->n;
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return 0;
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}
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static int tm_dscr_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (!MSR_TM_ACTIVE(target->thread.regs->msr))
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return -ENODATA;
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.tm_dscr, 0, sizeof(u64));
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return ret;
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}
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static int tm_dscr_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
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if (!cpu_has_feature(CPU_FTR_TM))
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return -ENODEV;
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if (!MSR_TM_ACTIVE(target->thread.regs->msr))
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return -ENODATA;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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&target->thread.tm_dscr, 0, sizeof(u64));
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return ret;
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}
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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/*
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@ -1565,6 +1710,9 @@ enum powerpc_regset {
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REGSET_TM_CVMX, /* TM checkpointed VMX registers */
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REGSET_TM_CVSX, /* TM checkpointed VSX registers */
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REGSET_TM_SPR, /* TM specific SPR registers */
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REGSET_TM_CTAR, /* TM checkpointed TAR register */
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REGSET_TM_CPPR, /* TM checkpointed PPR register */
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REGSET_TM_CDSCR, /* TM checkpointed DSCR register */
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#endif
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};
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@ -1626,6 +1774,21 @@ static const struct user_regset native_regsets[] = {
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
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},
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[REGSET_TM_CTAR] = {
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.core_note_type = NT_PPC_TM_CTAR, .n = 1,
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
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},
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[REGSET_TM_CPPR] = {
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.core_note_type = NT_PPC_TM_CPPR, .n = 1,
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
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},
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[REGSET_TM_CDSCR] = {
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.core_note_type = NT_PPC_TM_CDSCR, .n = 1,
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
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},
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#endif
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};
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@ -1878,6 +2041,21 @@ static const struct user_regset compat_regsets[] = {
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
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},
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[REGSET_TM_CTAR] = {
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.core_note_type = NT_PPC_TM_CTAR, .n = 1,
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
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},
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[REGSET_TM_CPPR] = {
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.core_note_type = NT_PPC_TM_CPPR, .n = 1,
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
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},
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[REGSET_TM_CDSCR] = {
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.core_note_type = NT_PPC_TM_CDSCR, .n = 1,
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.size = sizeof(u64), .align = sizeof(u64),
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.active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
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},
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#endif
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};
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