mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
Merge branch 'imx-drm-fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into staging-next
imx-drm fixes from Russell
This commit is contained in:
commit
c4784756a5
9 changed files with 196 additions and 62 deletions
|
@ -76,6 +76,7 @@ enum ipu_channel_irq {
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IPU_IRQ_EOS = 192,
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};
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int ipu_map_irq(struct ipu_soc *ipu, int irq);
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int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
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enum ipu_channel_irq irq);
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@ -114,8 +115,10 @@ struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
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void ipu_dc_put(struct ipu_dc *dc);
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int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
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u32 pixel_fmt, u32 width);
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void ipu_dc_enable(struct ipu_soc *ipu);
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void ipu_dc_enable_channel(struct ipu_dc *dc);
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void ipu_dc_disable_channel(struct ipu_dc *dc);
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void ipu_dc_disable(struct ipu_soc *ipu);
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/*
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* IPU Display Interface (di) functions
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@ -152,8 +155,10 @@ void ipu_dmfc_put(struct dmfc_channel *dmfc);
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struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
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void ipu_dp_put(struct ipu_dp *);
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int ipu_dp_enable(struct ipu_soc *ipu);
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int ipu_dp_enable_channel(struct ipu_dp *dp);
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void ipu_dp_disable_channel(struct ipu_dp *dp);
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void ipu_dp_disable(struct ipu_soc *ipu);
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int ipu_dp_setup_channel(struct ipu_dp *dp,
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enum ipu_color_space in, enum ipu_color_space out);
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int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
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@ -697,6 +697,12 @@ int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
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bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
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{
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return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
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{
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struct ipu_soc *ipu = channel->ipu;
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@ -714,6 +720,22 @@ int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
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int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(ms);
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ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
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while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
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{
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struct ipu_soc *ipu = channel->ipu;
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@ -934,15 +956,22 @@ static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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int ipu_map_irq(struct ipu_soc *ipu, int irq)
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{
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int virq;
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virq = irq_linear_revmap(ipu->domain, irq);
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if (!virq)
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virq = irq_create_mapping(ipu->domain, irq);
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return virq;
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}
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EXPORT_SYMBOL_GPL(ipu_map_irq);
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int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
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enum ipu_channel_irq irq_type)
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{
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int irq = irq_linear_revmap(ipu->domain, irq_type + channel->num);
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if (!irq)
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irq = irq_create_mapping(ipu->domain, irq_type + channel->num);
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return irq;
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return ipu_map_irq(ipu, irq_type + channel->num);
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
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@ -18,6 +18,7 @@
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include "../imx-drm.h"
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@ -111,6 +112,9 @@ struct ipu_dc_priv {
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struct device *dev;
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struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
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struct mutex mutex;
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struct completion comp;
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int dc_irq;
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int dp_irq;
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};
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static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
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@ -223,12 +227,16 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
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writel(0x0, dc->base + DC_WR_CH_ADDR);
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writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
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ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
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void ipu_dc_enable(struct ipu_soc *ipu)
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{
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ipu_module_enable(ipu, IPU_CONF_DC_EN);
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}
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EXPORT_SYMBOL_GPL(ipu_dc_enable);
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void ipu_dc_enable_channel(struct ipu_dc *dc)
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{
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int di;
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@ -242,41 +250,55 @@ void ipu_dc_enable_channel(struct ipu_dc *dc)
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}
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EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
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static irqreturn_t dc_irq_handler(int irq, void *dev_id)
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{
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struct ipu_dc *dc = dev_id;
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u32 reg;
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reg = readl(dc->base + DC_WR_CH_CONF);
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reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
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writel(reg, dc->base + DC_WR_CH_CONF);
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/* The Freescale BSP kernel clears DIx_COUNTER_RELEASE here */
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complete(&dc->priv->comp);
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return IRQ_HANDLED;
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}
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void ipu_dc_disable_channel(struct ipu_dc *dc)
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{
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struct ipu_dc_priv *priv = dc->priv;
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int irq, ret;
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u32 val;
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int irq = 0, timeout = 50;
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/* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
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if (dc->chno == 1)
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irq = IPU_IRQ_DC_FC_1;
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irq = priv->dc_irq;
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else if (dc->chno == 5)
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irq = IPU_IRQ_DP_SF_END;
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irq = priv->dp_irq;
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else
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return;
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/* should wait for the interrupt here */
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mdelay(50);
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init_completion(&priv->comp);
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enable_irq(irq);
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ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
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disable_irq(irq);
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if (ret <= 0) {
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dev_warn(priv->dev, "DC stop timeout after 50 ms\n");
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if (dc->di == 0)
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val = 0x00000002;
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else
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val = 0x00000020;
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/* Wait for DC triple buffer to empty */
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while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
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usleep_range(2000, 20000);
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timeout -= 2;
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if (timeout <= 0)
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break;
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val = readl(dc->base + DC_WR_CH_CONF);
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val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
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writel(val, dc->base + DC_WR_CH_CONF);
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}
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val = readl(dc->base + DC_WR_CH_CONF);
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val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
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writel(val, dc->base + DC_WR_CH_CONF);
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}
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EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
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void ipu_dc_disable(struct ipu_soc *ipu)
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{
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ipu_module_disable(ipu, IPU_CONF_DC_EN);
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}
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EXPORT_SYMBOL_GPL(ipu_dc_disable);
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static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
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int byte_num, int offset, int mask)
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{
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@ -343,7 +365,7 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
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struct ipu_dc_priv *priv;
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static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
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0x78, 0, 0x94, 0xb4};
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int i;
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int i, ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@ -364,6 +386,23 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
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priv->channels[i].base = priv->dc_reg + channel_offsets[i];
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}
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priv->dc_irq = ipu_map_irq(ipu, IPU_IRQ_DC_FC_1);
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if (!priv->dc_irq)
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return -EINVAL;
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ret = devm_request_irq(dev, priv->dc_irq, dc_irq_handler, 0, NULL,
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&priv->channels[1]);
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if (ret < 0)
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return ret;
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disable_irq(priv->dc_irq);
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priv->dp_irq = ipu_map_irq(ipu, IPU_IRQ_DP_SF_END);
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if (!priv->dp_irq)
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return -EINVAL;
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ret = devm_request_irq(dev, priv->dp_irq, dc_irq_handler, 0, NULL,
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&priv->channels[5]);
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if (ret < 0)
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return ret;
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disable_irq(priv->dp_irq);
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writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
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DC_WR_CH_CONF_PROG_DI_ID,
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priv->channels[1].base + DC_WR_CH_CONF);
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@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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}
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}
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if (!sig->clk_pol)
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if (sig->clk_pol)
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di_gen |= DI_GEN_POLARITY_DISP_CLK;
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ipu_di_write(di, di_gen, DI_GENERAL);
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|
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@ -28,7 +28,12 @@
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#define DMFC_GENERAL1 0x0014
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#define DMFC_GENERAL2 0x0018
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#define DMFC_IC_CTRL 0x001c
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#define DMFC_STAT 0x0020
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#define DMFC_WR_CHAN_ALT 0x0020
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#define DMFC_WR_CHAN_DEF_ALT 0x0024
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#define DMFC_DP_CHAN_ALT 0x0028
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#define DMFC_DP_CHAN_DEF_ALT 0x002c
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#define DMFC_GENERAL1_ALT 0x0030
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#define DMFC_STAT 0x0034
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#define DMFC_WR_CHAN_1_28 0
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#define DMFC_WR_CHAN_2_41 8
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@ -133,6 +138,20 @@ int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
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static void ipu_dmfc_wait_fifos(struct ipu_dmfc_priv *priv)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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while ((readl(priv->base + DMFC_STAT) & 0x02fff000) != 0x02fff000) {
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if (time_after(jiffies, timeout)) {
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dev_warn(priv->dev,
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"Timeout waiting for DMFC FIFOs to clear\n");
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break;
|
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}
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cpu_relax();
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}
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}
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|
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void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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|
@ -141,8 +160,10 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
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priv->use_count--;
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|
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if (!priv->use_count)
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if (!priv->use_count) {
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ipu_dmfc_wait_fifos(priv);
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ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
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}
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|
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if (priv->use_count < 0)
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priv->use_count = 0;
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|
|
|
@ -215,10 +215,9 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
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}
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EXPORT_SYMBOL_GPL(ipu_dp_setup_channel);
|
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|
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int ipu_dp_enable_channel(struct ipu_dp *dp)
|
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int ipu_dp_enable(struct ipu_soc *ipu)
|
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{
|
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struct ipu_flow *flow = to_flow(dp);
|
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struct ipu_dp_priv *priv = flow->priv;
|
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struct ipu_dp_priv *priv = ipu->dp_priv;
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|
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mutex_lock(&priv->mutex);
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|
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|
@ -227,15 +226,28 @@ int ipu_dp_enable_channel(struct ipu_dp *dp)
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|
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priv->use_count++;
|
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|
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if (dp->foreground) {
|
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u32 reg;
|
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mutex_unlock(&priv->mutex);
|
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|
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reg = readl(flow->base + DP_COM_CONF);
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reg |= DP_COM_CONF_FG_EN;
|
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writel(reg, flow->base + DP_COM_CONF);
|
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return 0;
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}
|
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EXPORT_SYMBOL_GPL(ipu_dp_enable);
|
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|
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ipu_srm_dp_sync_update(priv->ipu);
|
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}
|
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int ipu_dp_enable_channel(struct ipu_dp *dp)
|
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{
|
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struct ipu_flow *flow = to_flow(dp);
|
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struct ipu_dp_priv *priv = flow->priv;
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u32 reg;
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|
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if (!dp->foreground)
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return 0;
|
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|
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mutex_lock(&priv->mutex);
|
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|
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reg = readl(flow->base + DP_COM_CONF);
|
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reg |= DP_COM_CONF_FG_EN;
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writel(reg, flow->base + DP_COM_CONF);
|
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|
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ipu_srm_dp_sync_update(priv->ipu);
|
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|
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mutex_unlock(&priv->mutex);
|
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|
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|
@ -247,26 +259,39 @@ void ipu_dp_disable_channel(struct ipu_dp *dp)
|
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{
|
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struct ipu_flow *flow = to_flow(dp);
|
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struct ipu_dp_priv *priv = flow->priv;
|
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u32 reg, csc;
|
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|
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if (!dp->foreground)
|
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return;
|
||||
|
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mutex_lock(&priv->mutex);
|
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|
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reg = readl(flow->base + DP_COM_CONF);
|
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csc = reg & DP_COM_CONF_CSC_DEF_MASK;
|
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if (csc == DP_COM_CONF_CSC_DEF_FG)
|
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reg &= ~DP_COM_CONF_CSC_DEF_MASK;
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||||
|
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reg &= ~DP_COM_CONF_FG_EN;
|
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writel(reg, flow->base + DP_COM_CONF);
|
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|
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writel(0, flow->base + DP_FG_POS);
|
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ipu_srm_dp_sync_update(priv->ipu);
|
||||
|
||||
if (ipu_idmac_channel_busy(priv->ipu, IPUV3_CHANNEL_MEM_BG_SYNC))
|
||||
ipu_wait_interrupt(priv->ipu, IPU_IRQ_DP_SF_END, 50);
|
||||
|
||||
mutex_unlock(&priv->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);
|
||||
|
||||
void ipu_dp_disable(struct ipu_soc *ipu)
|
||||
{
|
||||
struct ipu_dp_priv *priv = ipu->dp_priv;
|
||||
|
||||
mutex_lock(&priv->mutex);
|
||||
|
||||
priv->use_count--;
|
||||
|
||||
if (dp->foreground) {
|
||||
u32 reg, csc;
|
||||
|
||||
reg = readl(flow->base + DP_COM_CONF);
|
||||
csc = reg & DP_COM_CONF_CSC_DEF_MASK;
|
||||
if (csc == DP_COM_CONF_CSC_DEF_FG)
|
||||
reg &= ~DP_COM_CONF_CSC_DEF_MASK;
|
||||
|
||||
reg &= ~DP_COM_CONF_FG_EN;
|
||||
writel(reg, flow->base + DP_COM_CONF);
|
||||
|
||||
writel(0, flow->base + DP_FG_POS);
|
||||
ipu_srm_dp_sync_update(priv->ipu);
|
||||
}
|
||||
|
||||
if (!priv->use_count)
|
||||
ipu_module_disable(priv->ipu, IPU_CONF_DP_EN);
|
||||
|
||||
|
@ -275,7 +300,7 @@ void ipu_dp_disable_channel(struct ipu_dp *dp)
|
|||
|
||||
mutex_unlock(&priv->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);
|
||||
EXPORT_SYMBOL_GPL(ipu_dp_disable);
|
||||
|
||||
struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow)
|
||||
{
|
||||
|
|
|
@ -185,6 +185,9 @@ void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
|
|||
int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
|
||||
int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
|
||||
|
||||
bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
|
||||
int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);
|
||||
|
||||
int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
|
||||
unsigned long base, u32 module, struct clk *ipu_clk);
|
||||
void ipu_di_exit(struct ipu_soc *ipu, int id);
|
||||
|
|
|
@ -60,24 +60,32 @@ struct ipu_crtc {
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|||
|
||||
static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
|
||||
{
|
||||
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
|
||||
|
||||
if (ipu_crtc->enabled)
|
||||
return;
|
||||
|
||||
ipu_di_enable(ipu_crtc->di);
|
||||
ipu_dc_enable_channel(ipu_crtc->dc);
|
||||
ipu_dc_enable(ipu);
|
||||
ipu_plane_enable(ipu_crtc->plane[0]);
|
||||
/* Start DC channel and DI after IDMAC */
|
||||
ipu_dc_enable_channel(ipu_crtc->dc);
|
||||
ipu_di_enable(ipu_crtc->di);
|
||||
|
||||
ipu_crtc->enabled = 1;
|
||||
}
|
||||
|
||||
static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
|
||||
{
|
||||
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
|
||||
|
||||
if (!ipu_crtc->enabled)
|
||||
return;
|
||||
|
||||
ipu_plane_disable(ipu_crtc->plane[0]);
|
||||
/* Stop DC channel and DI before IDMAC */
|
||||
ipu_dc_disable_channel(ipu_crtc->dc);
|
||||
ipu_di_disable(ipu_crtc->di);
|
||||
ipu_plane_disable(ipu_crtc->plane[0]);
|
||||
ipu_dc_disable(ipu);
|
||||
|
||||
ipu_crtc->enabled = 0;
|
||||
}
|
||||
|
@ -158,7 +166,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
|
|||
sig_cfg.Vsync_pol = 1;
|
||||
|
||||
sig_cfg.enable_pol = 1;
|
||||
sig_cfg.clk_pol = 1;
|
||||
sig_cfg.clk_pol = 0;
|
||||
sig_cfg.width = mode->hdisplay;
|
||||
sig_cfg.height = mode->vdisplay;
|
||||
sig_cfg.pixel_fmt = out_pixel_fmt;
|
||||
|
|
|
@ -239,6 +239,8 @@ int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
|
|||
|
||||
void ipu_plane_enable(struct ipu_plane *ipu_plane)
|
||||
{
|
||||
if (ipu_plane->dp)
|
||||
ipu_dp_enable(ipu_plane->ipu);
|
||||
ipu_dmfc_enable_channel(ipu_plane->dmfc);
|
||||
ipu_idmac_enable_channel(ipu_plane->ipu_ch);
|
||||
if (ipu_plane->dp)
|
||||
|
@ -257,6 +259,8 @@ void ipu_plane_disable(struct ipu_plane *ipu_plane)
|
|||
ipu_dp_disable_channel(ipu_plane->dp);
|
||||
ipu_idmac_disable_channel(ipu_plane->ipu_ch);
|
||||
ipu_dmfc_disable_channel(ipu_plane->dmfc);
|
||||
if (ipu_plane->dp)
|
||||
ipu_dp_disable(ipu_plane->ipu);
|
||||
}
|
||||
|
||||
static void ipu_plane_dpms(struct ipu_plane *ipu_plane, int mode)
|
||||
|
|
Loading…
Reference in a new issue