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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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arm64: dts: freescale: Add InnoComm i.MX8MM based WB15 SoM and EVK
Add the InnoComm i.MX8MM based WB15 SoM and its EVK. The WB15 is a half credit card sized board featuring: - i.MX8MM CPU - LPDDR4, 1GiB - eMMC, 8GiB - 1Gb Ethernet RGMII interface - WiFi 802.11 a/b/g/n/ac, Bluetooth 4.2 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Sascha Hauer
Shawn Guo
parent
19d0fc9e97
commit
c47d7b73c7
3 changed files with 627 additions and 0 deletions
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@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
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146
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts
Normal file
146
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts
Normal file
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@ -0,0 +1,146 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2018 Bang & Olufsen
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* Copyright 2022 Pengutronix
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*/
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/dts-v1/;
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#include "imx8mm-innocomm-wb15.dtsi"
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/ {
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model = "InnoComm WB15-EVK";
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compatible = "innocomm,wb15-evk", "fsl,imx8mm";
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chosen {
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stdout-path = &uart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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label = "debug";
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gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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reg_vsd_3v3: regulator-vsd-3v3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_ethphy: regulator-eth-phy {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy_reg>;
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regulator-name = "PHY_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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phy-supply = <®_ethphy>;
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};
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};
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};
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&uart2 {
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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disable-over-current;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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disable-over-current;
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status = "okay";
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};
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&usdhc2 {
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_vsd_3v3>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec: fec-grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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>;
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};
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pinctrl_fec_phy: fec-phy-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_fec_phy_reg: fec-phy-reg-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
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>;
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};
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pinctrl_gpio_leds: led-grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
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>;
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};
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pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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};
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480
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
Normal file
480
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
Normal file
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@ -0,0 +1,480 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2018 Bang & Olufsen
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*/
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#include "imx8mm.dtsi"
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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/ {
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reg_modem: regulator-modem {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_modem_regulator>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "epdev_on";
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gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_3v3_out: regulator-3v3-out {
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compatible = "regulator-fixed";
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regulator-name = "3V3_OUT";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&cpu_alert0 {
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temperature = <95000>;
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};
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&cpu_crit0 {
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temperature = <105000>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25000000 {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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regulators {
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buck1_reg: BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <850000>;
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rohm,dvs-idle-voltage = <850000>;
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rohm,dvs-suspend-voltage = <850000>;
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};
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buck2_reg: BUCK2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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buck3_reg: BUCK3 {
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// buck5 in datasheet
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regulator-name = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4_reg: BUCK4 {
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// buck6 in datasheet
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regulator-name = "buck4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5_reg: BUCK5 {
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// buck7 in datasheet
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regulator-name = "buck5";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6_reg: BUCK6 {
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// buck8 in datasheet
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regulator-name = "buck6";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: LDO1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: LDO2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: LDO3 {
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: LDO4 {
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regulator-name = "ldo4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5_reg: LDO5 {
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regulator-name = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo6_reg: LDO6 {
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regulator-name = "ldo6";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-1 = <&pinctrl_i2c3_gpio>;
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scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
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fsl,tx-deemph-gen1 = <0x2d>;
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fsl,tx-deemph-gen2 = <0xf>;
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status = "okay";
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
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<&clk IMX8MM_CLK_PCIE1_AUX>;
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clock-names = "pcie", "pcie_bus", "pcie_aux";
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fsl,max-link-speed = <1>;
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assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
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assigned-clock-rates = <10000000>, <250000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>;
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status = "okay";
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};
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&uart1 { /* BT */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MM_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm4349-bt";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_modem_bt>;
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device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
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host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
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shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
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vbat-supply = <®_3v3_out>;
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vddio-supply = <®_3v3_out>;
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clocks = <&osc_32k>;
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max-speed = <3000000>;
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clock-names = "extclk";
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};
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};
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&uart2 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_i2c1: i2c1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_gpio: i2c3-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
|
||||
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_modem_bt: modem-bt-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
|
||||
MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19
|
||||
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
|
||||
MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_modem_regulator: modem-reg-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmic-irq-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
|
||||
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdog-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue