mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

scsi: mpi3mr: Add mpi30 Rev-R headers and Kconfig 

This adds the Kconfig and mpi30 headers.

Link: https://lore.kernel.org/r/20210520152545.2710479-2-kashyap.desai@broadcom.com
Cc: sathya.prakash@broadcom.com
Cc: bvanassche@acm.org
Cc: hch@infradead.org
Reviewed-by: Hannes Reinecke <hare@suse.de>
Reviewed-by: Tomas Henzl <thenzl@redhat.com>
Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com>
Signed-off-by: Kashyap Desai <kashyap.desai@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Kashyap Desai 2021-05-20 20:55:22 +05:30 committed by Martin K. Petersen
parent f6b4142942
commit c4f7ac6461
7 changed files with 1851 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/scsi/Kconfig
View File

@ -482,6 +482,7 @@ config SCSI_ARCMSR
source "drivers/scsi/esas2r/Kconfig"
source "drivers/scsi/megaraid/Kconfig.megaraid"
source "drivers/scsi/mpt3sas/Kconfig"
source "drivers/scsi/mpi3mr/Kconfig"
source "drivers/scsi/smartpqi/Kconfig"
source "drivers/scsi/ufs/Kconfig"

1
drivers/scsi/Makefile
View File

@ -99,6 +99,7 @@ obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o
obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/
obj-$(CONFIG_MEGARAID_SAS) += megaraid/
obj-$(CONFIG_SCSI_MPT3SAS) += mpt3sas/
obj-$(CONFIG_SCSI_MPI3MR) += mpi3mr/
obj-$(CONFIG_SCSI_UFSHCD) += ufs/
obj-$(CONFIG_SCSI_ACARD) += atp870u.o
obj-$(CONFIG_SCSI_SUNESP) += esp_scsi.o sun_esp.o

7
drivers/scsi/mpi3mr/Kconfig Normal file
View File

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
config SCSI_MPI3MR
tristate "Broadcom MPI3 Storage Controller Device Driver"
depends on PCI && SCSI
help
MPI3 based Storage & RAID Controllers Driver.

216
drivers/scsi/mpi3mr/mpi/mpi30_image.h Normal file
View File

@ -0,0 +1,216 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2018-2021 Broadcom Inc. All rights reserved.
*
*/
#ifndef MPI30_IMAGE_H
#define MPI30_IMAGE_H 1
struct mpi3_comp_image_version {
__le16 build_num;
__le16 customer_id;
u8 phase_minor;
u8 phase_major;
u8 gen_minor;
u8 gen_major;
};
struct mpi3_hash_exclusion_format {
__le32 offset;
__le32 size;
};
#define MPI3_IMAGE_HASH_EXCUSION_NUM (4)
struct mpi3_component_image_header {
__le32 signature0;
__le32 load_address;
__le32 data_size;
__le32 start_offset;
__le32 signature1;
__le32 flash_offset;
__le32 image_size;
__le32 version_string_offset;
__le32 build_date_string_offset;
__le32 build_time_string_offset;
__le32 environment_variable_offset;
__le32 application_specific;
__le32 signature2;
__le32 header_size;
__le32 crc;
__le32 flags;
__le32 secondary_flash_offset;
__le32 etp_offset;
__le32 etp_size;
union mpi3_version_union rmc_interface_version;
union mpi3_version_union etp_interface_version;
struct mpi3_comp_image_version component_image_version;
struct mpi3_hash_exclusion_format hash_exclusion[MPI3_IMAGE_HASH_EXCUSION_NUM];
__le32 next_image_header_offset;
union mpi3_version_union security_version;
__le32 reserved84[31];
};
#define MPI3_IMAGE_HEADER_SIGNATURE0_MPI3 (0xeb00003e)
#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_INVALID (0x00000000)
#define MPI3_IMAGE_HEADER_SIGNATURE1_APPLICATION (0x20505041)
#define MPI3_IMAGE_HEADER_SIGNATURE1_FIRST_MUTABLE (0x20434d46)
#define MPI3_IMAGE_HEADER_SIGNATURE1_BSP (0x20505342)
#define MPI3_IMAGE_HEADER_SIGNATURE1_ROM_BIOS (0x534f4942)
#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_X64 (0x4d494948)
#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_ARM (0x41494948)
#define MPI3_IMAGE_HEADER_SIGNATURE1_CPLD (0x444c5043)
#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053)
#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147)
#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504c4250)
#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI (0x00000010)
#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA (0x00000008)
#define MPI3_IMAGE_HEADER_FLAGS_REQUIRES_ACTIVATION (0x00000004)
#define MPI3_IMAGE_HEADER_FLAGS_COMPRESSED (0x00000002)
#define MPI3_IMAGE_HEADER_FLAGS_FLASH (0x00000001)
#define MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET (0x00)
#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_OFFSET (0x04)
#define MPI3_IMAGE_HEADER_DATA_SIZE_OFFSET (0x08)
#define MPI3_IMAGE_HEADER_START_OFFSET_OFFSET (0x0c)
#define MPI3_IMAGE_HEADER_SIGNATURE1_OFFSET (0x10)
#define MPI3_IMAGE_HEADER_FLASH_OFFSET_OFFSET (0x14)
#define MPI3_IMAGE_HEADER_FLASH_SIZE_OFFSET (0x18)
#define MPI3_IMAGE_HEADER_VERSION_STRING_OFFSET_OFFSET (0x1c)
#define MPI3_IMAGE_HEADER_BUILD_DATE_STRING_OFFSET_OFFSET (0x20)
#define MPI3_IMAGE_HEADER_BUILD_TIME_OFFSET_OFFSET (0x24)
#define MPI3_IMAGE_HEADER_ENVIROMENT_VAR_OFFSET_OFFSET (0x28)
#define MPI3_IMAGE_HEADER_APPLICATION_SPECIFIC_OFFSET (0x2c)
#define MPI3_IMAGE_HEADER_SIGNATURE2_OFFSET (0x30)
#define MPI3_IMAGE_HEADER_HEADER_SIZE_OFFSET (0x34)
#define MPI3_IMAGE_HEADER_CRC_OFFSET (0x38)
#define MPI3_IMAGE_HEADER_FLAGS_OFFSET (0x3c)
#define MPI3_IMAGE_HEADER_SECONDARY_FLASH_OFFSET_OFFSET (0x40)
#define MPI3_IMAGE_HEADER_ETP_OFFSET_OFFSET (0x44)
#define MPI3_IMAGE_HEADER_ETP_SIZE_OFFSET (0x48)
#define MPI3_IMAGE_HEADER_RMC_INTERFACE_VER_OFFSET (0x4c)
#define MPI3_IMAGE_HEADER_ETP_INTERFACE_VER_OFFSET (0x50)
#define MPI3_IMAGE_HEADER_COMPONENT_IMAGE_VER_OFFSET (0x54)
#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5c)
#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7c)
#define MPI3_IMAGE_HEADER_SIZE (0x100)
struct mpi3_extended_image_header {
u8 image_type;
u8 reserved01[3];
__le32 checksum;
__le32 image_size;
__le32 next_image_header_offset;
__le32 reserved10[4];
__le32 identify_string[8];
};
#define MPI3_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
#define MPI3_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
#define MPI3_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0c)
#define MPI3_EXT_IMAGE_HEADER_SIZE (0x40)
#define MPI3_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
#define MPI3_EXT_IMAGE_TYPE_NVDATA (0x03)
#define MPI3_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
#define MPI3_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
#define MPI3_EXT_IMAGE_TYPE_RDE (0x0a)
#define MPI3_EXT_IMAGE_TYPE_AUXILIARY_PROCESSOR (0x0b)
#define MPI3_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
#define MPI3_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xff)
struct mpi3_supported_device {
__le16 device_id;
__le16 vendor_id;
__le16 device_id_mask;
__le16 reserved06;
u8 low_pci_rev;
u8 high_pci_rev;
__le16 reserved0a;
__le32 reserved0c;
};
#ifndef MPI3_SUPPORTED_DEVICE_MAX
#define MPI3_SUPPORTED_DEVICE_MAX (1)
#endif
struct mpi3_supported_devices_data {
u8 image_version;
u8 reserved01;
u8 num_devices;
u8 reserved03;
__le32 reserved04;
struct mpi3_supported_device supported_device[MPI3_SUPPORTED_DEVICE_MAX];
};
#ifndef MPI3_ENCRYPTED_HASH_MAX
#define MPI3_ENCRYPTED_HASH_MAX (1)
#endif
struct mpi3_encrypted_hash_entry {
u8 hash_image_type;
u8 hash_algorithm;
u8 encryption_algorithm;
u8 reserved03;
__le32 reserved04;
__le32 encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];
};
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03)
#define MPI3_HASH_ALGORITHM_VERSION_MASK (0xe0)
#define MPI3_HASH_ALGORITHM_VERSION_NONE (0x00)
#define MPI3_HASH_ALGORITHM_VERSION_SHA1 (0x20)
#define MPI3_HASH_ALGORITHM_VERSION_SHA2 (0x40)
#define MPI3_HASH_ALGORITHM_VERSION_SHA3 (0x60)
#define MPI3_HASH_ALGORITHM_SIZE_MASK (0x1f)
#define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00)
#define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01)
#define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02)
#define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00)
#define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01)
#define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02)
#define MPI3_ENCRYPTION_ALGORITHM_RSA1024 (0x03)
#define MPI3_ENCRYPTION_ALGORITHM_RSA2048 (0x04)
#define MPI3_ENCRYPTION_ALGORITHM_RSA4096 (0x05)
#define MPI3_ENCRYPTION_ALGORITHM_RSA3072 (0x06)
#ifndef MPI3_PUBLIC_KEY_MAX
#define MPI3_PUBLIC_KEY_MAX (1)
#endif
struct mpi3_encrypted_key_with_hash_entry {
u8 hash_image_type;
u8 hash_algorithm;
u8 encryption_algorithm;
u8 reserved03;
__le32 reserved04;
__le32 public_key[MPI3_PUBLIC_KEY_MAX];
__le32 encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];
};
#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
#define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1)
#endif
struct mpi3_encrypted_hash_data {
u8 image_version;
u8 num_hash;
__le16 reserved02;
__le32 reserved04;
struct mpi3_encrypted_hash_entry encrypted_hash_entry[MPI3_ENCRYPTED_HASH_ENTRY_MAX];
};
#ifndef MPI3_AUX_PROC_DATA_MAX
#define MPI3_AUX_PROC_DATA_MAX (1)
#endif
struct mpi3_aux_processor_data {
u8 boot_method;
u8 num_load_addr;
u8 reserved02;
u8 type;
__le32 version;
__le32 load_address[8];
__le32 reserved28[22];
__le32 aux_processor_data[MPI3_AUX_PROC_DATA_MAX];
};
#define MPI3_AUX_PROC_DATA_OFFSET (0x80)
#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_MSG (0x00)
#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_DOORBELL (0x01)
#define MPI3_AUXPROCESSOR_BOOT_METHOD_COMPONENT (0x02)
#define MPI3_AUXPROCESSOR_TYPE_ARM_A15 (0x00)
#define MPI3_AUXPROCESSOR_TYPE_ARM_M0 (0x01)
#define MPI3_AUXPROCESSOR_TYPE_ARM_R4 (0x02)
#endif

159
drivers/scsi/mpi3mr/mpi/mpi30_init.h Normal file
View File

@ -0,0 +1,159 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
*
*/
#ifndef MPI30_INIT_H
#define MPI30_INIT_H 1
struct mpi3_scsi_io_cdb_eedp32 {
u8 cdb[20];
__be32 primary_reference_tag;
__le16 primary_application_tag;
__le16 primary_application_tag_mask;
__le32 transfer_length;
};
union mpi3_scso_io_cdb_union {
u8 cdb32[32];
struct mpi3_scsi_io_cdb_eedp32 eedp32;
struct mpi3_sge_common sge;
};
struct mpi3_scsi_io_request {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 change_count;
__le16 dev_handle;
__le32 flags;
__le32 skip_count;
__le32 data_length;
u8 lun[8];
union mpi3_scso_io_cdb_union cdb;
union mpi3_sge_union sgl[4];
};
#define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
#define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
#define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
#define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
#define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000)
#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ACAQ (0x04000000)
#define MPI3_SCSIIO_FLAGS_CMDPRI_MASK (0x00f00000)
#define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT (20)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000c0000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER (0x00000000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE (0x00040000)
#define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ (0x00080000)
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK (0x00030000)
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000)
#define MPI3_SCSIIO_METASGL_INDEX (3)
struct mpi3_scsi_io_reply {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
u8 scsi_status;
u8 scsi_state;
__le16 dev_handle;
__le32 transfer_count;
__le32 sense_count;
__le32 response_data;
__le16 task_tag;
__le16 scsi_status_qualifier;
__le32 eedp_error_offset;
__le16 eedp_observed_app_tag;
__le16 eedp_observed_guard;
__le32 eedp_observed_ref_tag;
__le64 sense_data_buffer_address;
};
#define MPI3_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID (0x01)
#define MPI3_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID (0x02)
#define MPI3_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID (0x04)
#define MPI3_SCSI_STATUS_GOOD (0x00)
#define MPI3_SCSI_STATUS_CHECK_CONDITION (0x02)
#define MPI3_SCSI_STATUS_CONDITION_MET (0x04)
#define MPI3_SCSI_STATUS_BUSY (0x08)
#define MPI3_SCSI_STATUS_INTERMEDIATE (0x10)
#define MPI3_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
#define MPI3_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
#define MPI3_SCSI_STATUS_COMMAND_TERMINATED (0x22)
#define MPI3_SCSI_STATUS_TASK_SET_FULL (0x28)
#define MPI3_SCSI_STATUS_ACA_ACTIVE (0x30)
#define MPI3_SCSI_STATUS_TASK_ABORTED (0x40)
#define MPI3_SCSI_STATE_SENSE_MASK (0x03)
#define MPI3_SCSI_STATE_SENSE_VALID (0x00)
#define MPI3_SCSI_STATE_SENSE_FAILED (0x01)
#define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY (0x02)
#define MPI3_SCSI_STATE_SENSE_NOT_AVAILABLE (0x03)
#define MPI3_SCSI_STATE_NO_SCSI_STATUS (0x04)
#define MPI3_SCSI_STATE_TERMINATED (0x08)
#define MPI3_SCSI_STATE_RESPONSE_DATA_VALID (0x10)
#define MPI3_SCSI_RSP_RESPONSECODE_MASK (0x000000ff)
#define MPI3_SCSI_RSP_RESPONSECODE_SHIFT (0)
#define MPI3_SCSI_RSP_ARI2_MASK (0x0000ff00)
#define MPI3_SCSI_RSP_ARI2_SHIFT (8)
#define MPI3_SCSI_RSP_ARI1_MASK (0x00ff0000)
#define MPI3_SCSI_RSP_ARI1_SHIFT (16)
#define MPI3_SCSI_RSP_ARI0_MASK (0xff000000)
#define MPI3_SCSI_RSP_ARI0_SHIFT (24)
#define MPI3_SCSI_TASKTAG_UNKNOWN (0xffff)
struct mpi3_scsi_task_mgmt_request {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 change_count;
__le16 dev_handle;
__le16 task_host_tag;
u8 task_type;
u8 reserved0f;
__le16 task_request_queue_id;
__le16 reserved12;
__le32 reserved14;
u8 lun[8];
};
#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02)
#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a)
#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b)
struct mpi3_scsi_task_mgmt_reply {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
__le32 termination_count;
__le32 response_data;
__le32 reserved18;
};
#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80)
#endif

1004
drivers/scsi/mpi3mr/mpi/mpi30_ioc.h Normal file
View File

File diff suppressed because it is too large Load Diff

463
drivers/scsi/mpi3mr/mpi/mpi30_transport.h Normal file
View File

@ -0,0 +1,463 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
*
*/
#ifndef MPI30_TRANSPORT_H
#define MPI30_TRANSPORT_H 1
struct mpi3_version_struct {
u8 dev;
u8 unit;
u8 minor;
u8 major;
};
union mpi3_version_union {
struct mpi3_version_struct mpi3_version;
__le32 word;
};
#define MPI3_VERSION_MAJOR (3)
#define MPI3_VERSION_MINOR (0)
#define MPI3_VERSION_UNIT (0)
#define MPI3_VERSION_DEV (18)
struct mpi3_sysif_oper_queue_indexes {
__le16 producer_index;
__le16 reserved02;
__le16 consumer_index;
__le16 reserved06;
};
struct mpi3_sysif_registers {
__le64 ioc_information;
union mpi3_version_union version;
__le32 reserved0c[2];
__le32 ioc_configuration;
__le32 reserved18;
__le32 ioc_status;
__le32 reserved20;
__le32 admin_queue_num_entries;
__le64 admin_request_queue_address;
__le64 admin_reply_queue_address;
__le32 reserved38[2];
__le32 coalesce_control;
__le32 reserved44[1007];
__le16 admin_request_queue_pi;
__le16 reserved1002;
__le16 admin_reply_queue_ci;
__le16 reserved1006;
struct mpi3_sysif_oper_queue_indexes oper_queue_indexes[383];
__le32 reserved1c00;
__le32 write_sequence;
__le32 host_diagnostic;
__le32 reserved1c0c;
__le32 fault;
__le32 fault_info[3];
__le32 reserved1c20[4];
__le64 hcb_address;
__le32 hcb_size;
__le32 reserved1c3c;
__le32 reply_free_host_index;
__le32 sense_buffer_free_host_index;
__le32 reserved1c48[2];
__le64 diag_rw_data;
__le64 diag_rw_address;
__le16 diag_rw_control;
__le16 diag_rw_status;
__le32 reserved1c64[35];
__le32 scratchpad[4];
__le32 reserved1d00[192];
__le32 device_assigned_registers[2048];
};
#define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
#define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24)
#define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000)
#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20)
#define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000f0000)
#define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000c000)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000)
#define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN (0x00002000)
#define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010)
#define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001)
#define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001c)
#define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000c)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008)
#define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002)
#define MPI3_SYSIF_IOC_STATUS_READY (0x00000001)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0fff)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0fff0000)
#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16)
#define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028)
#define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002c)
#define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030)
#define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034)
#define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xc0000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xc0000000)
#define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x30000000)
#define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_MASK (0x00ff0000)
#define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_SHIFT (16)
#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000ff00)
#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8)
#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000ff)
#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0)
#define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000)
#define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004)
#define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008)
#define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(n) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((n) - 1) * 8))
#define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100c)
#define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(n) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((n) - 1) * 8))
#define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001c04)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000f)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xf)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xb)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xd)
#define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001c08)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_FLASH_RCVRY_RESET (0x00000200)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700)
#define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080)
#define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040)
#define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020)
#define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010)
#define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008)
#define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004)
#define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002)
#define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001)
#define MPI3_SYSIF_FAULT_OFFSET (0x00001c10)
#define MPI3_SYSIF_FAULT_FUNC_AREA_MASK (0xff000000)
#define MPI3_SYSIF_FAULT_FUNC_AREA_SHIFT (24)
#define MPI3_SYSIF_FAULT_FUNC_AREA_MPI_DEFINED (0x00000000)
#define MPI3_SYSIF_FAULT_CODE_MASK (0x0000ffff)
#define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000f000)
#define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000f001)
#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000f002)
#define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000f003)
#define MPI3_SYSIF_FAULT_CODE_SAFE_MODE_EXIT (0x0000f004)
#define MPI3_SYSIF_FAULT_CODE_FACTORY_RESET (0x0000f005)
#define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14)
#define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18)
#define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c)
#define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001c30)
#define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001c34)
#define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001c38)
#define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xfffff000)
#define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12)
#define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001)
#define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001c40)
#define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001c44)
#define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001c50)
#define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001c54)
#define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001c58)
#define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001c5c)
#define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001c60)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020)
#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030)
#define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004)
#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002)
#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000)
#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002)
#define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001)
#define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001c62)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000e)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004)
#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006)
#define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001)
#define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001cf0)
#define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001cf4)
#define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001cf8)
#define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001cfc)
#define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000)
#define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60)
struct mpi3_default_reply_descriptor {
__le32 descriptor_type_dependent1[2];
__le16 request_queue_ci;
__le16 request_queue_id;
__le16 descriptor_type_dependent2;
__le16 reply_flags;
};
#define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xf000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000)
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000)
struct mpi3_address_reply_descriptor {
__le64 reply_frame_address;
__le16 request_queue_ci;
__le16 request_queue_id;
__le16 reserved0c;
__le16 reply_flags;
};
struct mpi3_success_reply_descriptor {
__le32 reserved00[2];
__le16 request_queue_ci;
__le16 request_queue_id;
__le16 host_tag;
__le16 reply_flags;
};
struct mpi3_target_command_buffer_reply_descriptor {
__le32 reserved00;
__le16 initiator_dev_handle;
u8 phy_num;
u8 reserved07;
__le16 request_queue_ci;
__le16 request_queue_id;
__le16 io_index;
__le16 reply_flags;
};
struct mpi3_status_reply_descriptor {
__le16 ioc_status;
__le16 reserved02;
__le32 ioc_log_info;
__le16 request_queue_ci;
__le16 request_queue_id;
__le16 host_tag;
__le16 reply_flags;
};
#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7fff)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xf0000000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000)
#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0fffffff)
union mpi3_reply_descriptors_union {
struct mpi3_default_reply_descriptor default_reply;
struct mpi3_address_reply_descriptor address_reply;
struct mpi3_success_reply_descriptor success;
struct mpi3_target_command_buffer_reply_descriptor target_command_buffer;
struct mpi3_status_reply_descriptor status;
__le32 words[4];
};
struct mpi3_sge_common {
__le64 address;
__le32 length;
u8 reserved0c[3];
u8 flags;
};
struct mpi3_sge_bit_bucket {
__le64 reserved00;
__le32 length;
u8 reserved0c[3];
u8 flags;
};
struct mpi3_sge_extended_eedp {
u8 user_data_size;
u8 reserved01;
__le16 eedp_flags;
__le32 secondary_reference_tag;
__le16 secondary_application_tag;
__le16 application_tag_translation_mask;
__le16 reserved0c;
u8 extended_operation;
u8 flags;
};
union mpi3_sge_union {
struct mpi3_sge_common simple;
struct mpi3_sge_common chain;
struct mpi3_sge_common last_chain;
struct mpi3_sge_bit_bucket bit_bucket;
struct mpi3_sge_extended_eedp eedp;
__le32 words[4];
};
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xf0)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30)
#define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xf0)
#define MPI3_SGE_FLAGS_END_OF_LIST (0x08)
#define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04)
#define MPI3_SGE_FLAGS_DLAS_MASK (0x03)
#define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00)
#define MPI3_SGE_FLAGS_DLAS_IOC_DDR (0x01)
#define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02)
#define MPI3_SGE_EXT_OPER_EEDP (0x00)
#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000)
#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000)
#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000)
#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000)
#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800)
#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400)
#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200)
#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100)
#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00c0)
#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040)
#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080)
#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00c0)
#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030)
#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000)
#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010)
#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020)
#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008)
#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007)
#define MPI3_EEDPFLAGS_EEDP_OP_NOOP (0x0000)
#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001)
#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002)
#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003)
#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004)
#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006)
#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007)
#define MPI3_EEDP_UDS_512 (0x01)
#define MPI3_EEDP_UDS_520 (0x02)
#define MPI3_EEDP_UDS_4080 (0x03)
#define MPI3_EEDP_UDS_4088 (0x04)
#define MPI3_EEDP_UDS_4096 (0x05)
#define MPI3_EEDP_UDS_4104 (0x06)
#define MPI3_EEDP_UDS_4160 (0x07)
struct mpi3_request_header {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 change_count;
__le16 function_dependent;
};
struct mpi3_default_reply {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
};
#define MPI3_HOST_TAG_INVALID (0xffff)
#define MPI3_FUNCTION_IOC_FACTS (0x01)
#define MPI3_FUNCTION_IOC_INIT (0x02)
#define MPI3_FUNCTION_PORT_ENABLE (0x03)
#define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04)
#define MPI3_FUNCTION_EVENT_ACK (0x05)
#define MPI3_FUNCTION_CI_DOWNLOAD (0x06)
#define MPI3_FUNCTION_CI_UPLOAD (0x07)
#define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08)
#define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09)
#define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0a)
#define MPI3_FUNCTION_CONFIG (0x10)
#define MPI3_FUNCTION_SCSI_IO (0x20)
#define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21)
#define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22)
#define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24)
#define MPI3_FUNCTION_TARGET_ASSIST (0x30)
#define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31)
#define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32)
#define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33)
#define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34)
#define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70)
#define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71)
#define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72)
#define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73)
#define MPI3_FUNCTION_TOOLBOX (0x80)
#define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81)
#define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82)
#define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83)
#define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xc0)
#define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xef)
#define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xf0)
#define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xff)
#define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000)
#define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000)
#define MPI3_IOCSTATUS_STATUS_MASK (0x7fff)
#define MPI3_IOCSTATUS_SUCCESS (0x0000)
#define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001)
#define MPI3_IOCSTATUS_BUSY (0x0002)
#define MPI3_IOCSTATUS_INVALID_SGL (0x0003)
#define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004)
#define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
#define MPI3_IOCSTATUS_INVALID_FIELD (0x0007)
#define MPI3_IOCSTATUS_INVALID_STATE (0x0008)
#define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a)
#define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b)
#define MPI3_IOCSTATUS_FAILURE (0x001f)
#define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
#define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
#define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
#define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
#define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
#define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
#define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
#define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041)
#define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
#define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
#define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
#define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
#define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
#define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
#define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
#define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
#define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a)
#define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b)
#define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c)
#define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004d)
#define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e)
#define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f)
#define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
#define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063)
#define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
#define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
#define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a)
#define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d)
#define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e)
#define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f)
#define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
#define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
#define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
#define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
#define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0)
#define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00b0)
#define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00b1)
#define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00b2)
#define MPI3_IOCSTATUS_CI_UPDATE_PENDING (0x00b3)
#define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00c0)
#define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0f00)
#define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0f01)
#define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0f02)
#define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0f03)
#define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0f04)
#define MPI3_IOCLOGINFO_TYPE_MASK (0xf0000000)
#define MPI3_IOCLOGINFO_TYPE_SHIFT (28)
#define MPI3_IOCLOGINFO_TYPE_NONE (0x0)
#define MPI3_IOCLOGINFO_TYPE_SAS (0x3)
#define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0fffffff)
#endif