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drm/i915/snps: convert to drm device based logging
Prefer drm device based logging. Do some dev_priv->i915 conversions while at it. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ca6908452a63bd74a9c9d75ecd295182c80c7205.1642769982.git.jani.nikula@intel.com
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17dd7b896a
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c5274e86da
1 changed files with 15 additions and 14 deletions
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@ -24,18 +24,18 @@
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* since it is not handled by the shared DPLL framework as on other platforms.
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*/
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void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
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void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
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{
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enum phy phy;
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for_each_phy_masked(phy, ~0) {
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if (!intel_phy_is_snps(dev_priv, phy))
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if (!intel_phy_is_snps(i915, phy))
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continue;
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if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
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if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
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DG2_PHY_DP_TX_ACK_MASK, 25))
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DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
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phy);
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drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
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phy);
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}
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}
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@ -776,6 +776,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
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int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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const struct intel_mpllb_state * const *tables;
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int i;
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@ -787,8 +788,8 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
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* until we have a proper algorithm under a valid
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* license.
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*/
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DRM_DEBUG_KMS("Can't support HDMI link rate %d\n",
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crtc_state->port_clock);
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drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
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crtc_state->port_clock);
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return -EINVAL;
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}
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}
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@ -855,7 +856,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
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* dp_mpllb_state interface signal.
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*/
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if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
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DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
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drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
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/*
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* 11. If the frequency will result in a change to the voltage
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@ -868,8 +869,8 @@ void intel_mpllb_enable(struct intel_encoder *encoder,
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void intel_mpllb_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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enum phy phy = intel_port_to_phy(i915, encoder->port);
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i915_reg_t enable_reg = (phy <= PHY_D ?
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DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
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@ -882,21 +883,21 @@ void intel_mpllb_disable(struct intel_encoder *encoder)
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*/
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/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
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intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0);
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intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0);
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/*
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* 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
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* This will allow the PLL to stop running.
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*/
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intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy),
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intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy),
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SNPS_PHY_MPLLB_FORCE_EN, 0);
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/*
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* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
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* (dp_txX_ack) that the new transmitter setting request is completed.
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*/
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if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5))
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DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
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if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
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drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
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/*
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* 6. If the frequency will result in a change to the voltage
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