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mmc: dw_mmc: exynos: add variable delay tuning sequence
Implements variable delay tuning. In this change, exynos host can determine the correct sampling point for the HS200 and SDR104 speed mode. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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1 changed files with 124 additions and 0 deletions
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@ -14,8 +14,10 @@
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/mmc/mmc.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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@ -231,6 +233,127 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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return 0;
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}
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static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
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{
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return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
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}
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static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
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{
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u32 clksel;
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clksel = mci_readl(host, CLKSEL);
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clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
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mci_writel(host, CLKSEL, clksel);
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}
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static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
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{
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u32 clksel;
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u8 sample;
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clksel = mci_readl(host, CLKSEL);
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sample = (clksel + 1) & 0x7;
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clksel = (clksel & ~0x7) | sample;
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mci_writel(host, CLKSEL, clksel);
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return sample;
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}
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static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
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{
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const u8 iter = 8;
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u8 __c;
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s8 i, loc = -1;
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for (i = 0; i < iter; i++) {
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__c = ror8(candiates, i);
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if ((__c & 0xc7) == 0xc7) {
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loc = i;
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goto out;
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}
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}
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for (i = 0; i < iter; i++) {
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__c = ror8(candiates, i);
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if ((__c & 0x83) == 0x83) {
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loc = i;
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goto out;
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}
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}
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out:
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return loc;
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}
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static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
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struct dw_mci_tuning_data *tuning_data)
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{
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struct dw_mci *host = slot->host;
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struct mmc_host *mmc = slot->mmc;
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const u8 *blk_pattern = tuning_data->blk_pattern;
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u8 *blk_test;
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unsigned int blksz = tuning_data->blksz;
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u8 start_smpl, smpl, candiates = 0;
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s8 found = -1;
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int ret = 0;
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blk_test = kmalloc(blksz, GFP_KERNEL);
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if (!blk_test)
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return -ENOMEM;
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start_smpl = dw_mci_exynos_get_clksmpl(host);
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do {
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struct mmc_request mrq = {NULL};
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struct mmc_command cmd = {0};
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struct mmc_command stop = {0};
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struct mmc_data data = {0};
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struct scatterlist sg;
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cmd.opcode = opcode;
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cmd.arg = 0;
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cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
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stop.opcode = MMC_STOP_TRANSMISSION;
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stop.arg = 0;
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stop.flags = MMC_RSP_R1B | MMC_CMD_AC;
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data.blksz = blksz;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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data.sg = &sg;
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data.sg_len = 1;
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sg_init_one(&sg, blk_test, blksz);
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mrq.cmd = &cmd;
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mrq.stop = &stop;
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mrq.data = &data;
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host->mrq = &mrq;
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mci_writel(host, TMOUT, ~0);
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smpl = dw_mci_exynos_move_next_clksmpl(host);
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mmc_wait_for_req(mmc, &mrq);
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if (!cmd.error && !data.error) {
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if (!memcmp(blk_pattern, blk_test, blksz))
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candiates |= (1 << smpl);
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} else {
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dev_dbg(host->dev,
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"Tuning error: cmd.error:%d, data.error:%d\n",
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cmd.error, data.error);
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}
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} while (start_smpl != smpl);
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found = dw_mci_exynos_get_best_clksmpl(candiates);
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if (found >= 0)
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dw_mci_exynos_set_clksmpl(host, found);
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else
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ret = -EIO;
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kfree(blk_test);
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return ret;
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}
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/* Common capabilities of Exynos4/Exynos5 SoC */
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static unsigned long exynos_dwmmc_caps[4] = {
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MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
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@ -247,6 +370,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
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.prepare_command = dw_mci_exynos_prepare_command,
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.set_ios = dw_mci_exynos_set_ios,
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.parse_dt = dw_mci_exynos_parse_dt,
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.execute_tuning = dw_mci_exynos_execute_tuning,
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};
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static const struct of_device_id dw_mci_exynos_match[] = {
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