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[ALSA] ice1724 - Misc fixes for Prodigy192
- always set 256fs in SPDIF master clock mode - disable deemphasis filter in AK4114 for Prodigy192 Signed-off-by: Pavel Hofman <dustin@seznam.cz> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
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2 changed files with 16 additions and 1 deletions
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@ -1666,7 +1666,12 @@ static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
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spin_lock_irq(&ice->reg_lock);
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oval = inb(ICEMT1724(ice, RATE));
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if (ucontrol->value.enumerated.item[0] == spdif) {
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unsigned char i2s_oval;
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outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
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/* setting 256fs */
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i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
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outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X,
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ICEMT1724(ice, I2S_FORMAT));
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} else {
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rate = rates[ucontrol->value.integer.value[0] % 15];
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if (rate <= get_max_rate(ice)) {
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@ -26,6 +26,13 @@
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* CCLK (pin 34) -- GPIO9 pin 76
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* CSN (pin 35) -- GPIO8 pin 75
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* - output data Mode 7 (24bit, I2S, slave)
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* - both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which
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* outputs master clock to SPMCLKIN of ice1724.
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* Experimentally I found out that only a combination of
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* OCKS0=1, OCKS1=1 (128fs, 64fs output) and ice1724 -
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* VT1724_MT_I2S_MCLK_128X=0 (256fs input) yields correct
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* sampling rate. That means the the FPGA doubles the
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* MCK01 rate.
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*
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* Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>
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* Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>
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@ -714,7 +721,10 @@ static int prodigy192_ak4114_init(struct snd_ice1712 *ice)
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{
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static const unsigned char ak4114_init_vals[] = {
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AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,
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AK4114_DIF_I24I2S, /* ice1724 expects I2S and provides clock */
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/* ice1724 expects I2S and provides clock,
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* DEM0 disables the deemphasis filter
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*/
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AK4114_DIF_I24I2S | AK4114_DEM0 ,
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AK4114_TX1E,
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AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */
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0,
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