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[PATCH] forcedeth: add recoverable error support
This patch adds support to recover from a previously fatal MAC error. In the past the MAC would be hung on an internal fatal error. On new chipsets, the MAC has the ability to enter a non-fatal state and allow the driver to re-init it. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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7e680c22c0
commit
c5cf9101fe
1 changed files with 74 additions and 4 deletions
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@ -111,6 +111,7 @@
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* 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
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* 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
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* 0.58: 30 Oct 2006: Added support for sideband management unit.
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* 0.59: 30 Oct 2006: Added support for recoverable error.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -127,7 +128,7 @@
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#else
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#define DRIVERNAPI
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#endif
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#define FORCEDETH_VERSION "0.58"
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#define FORCEDETH_VERSION "0.59"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -180,7 +181,7 @@
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enum {
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NvRegIrqStatus = 0x000,
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#define NVREG_IRQSTAT_MIIEVENT 0x040
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#define NVREG_IRQSTAT_MASK 0x1ff
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#define NVREG_IRQSTAT_MASK 0x81ff
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NvRegIrqMask = 0x004,
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#define NVREG_IRQ_RX_ERROR 0x0001
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#define NVREG_IRQ_RX 0x0002
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@ -191,15 +192,16 @@ enum {
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#define NVREG_IRQ_LINK 0x0040
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#define NVREG_IRQ_RX_FORCED 0x0080
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#define NVREG_IRQ_TX_FORCED 0x0100
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#define NVREG_IRQ_RECOVER_ERROR 0x8000
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#define NVREG_IRQMASK_THROUGHPUT 0x00df
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#define NVREG_IRQMASK_CPU 0x0040
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#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
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#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
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#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
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#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
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#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
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NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
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NVREG_IRQ_TX_FORCED))
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NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
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NvRegUnknownSetupReg6 = 0x008,
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#define NVREG_UNKSETUP6_VAL 3
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@ -718,6 +720,7 @@ struct fe_priv {
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unsigned int phy_model;
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u16 gigabit;
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int intr_test;
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int recover_error;
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/* General data: RO fields */
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dma_addr_t ring_addr;
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@ -2455,6 +2458,23 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
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printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
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dev->name, events);
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}
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if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
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spin_lock(&np->lock);
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/* disable interrupts on the nic */
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if (!(np->msi_flags & NV_MSI_X_ENABLED))
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writel(0, base + NvRegIrqMask);
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else
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writel(np->irqmask, base + NvRegIrqMask);
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pci_push(base);
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if (!np->in_shutdown) {
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np->nic_poll_irq = np->irqmask;
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np->recover_error = 1;
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mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
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}
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spin_unlock(&np->lock);
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break;
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}
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#ifdef CONFIG_FORCEDETH_NAPI
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if (events & NVREG_IRQ_RX_ALL) {
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netif_rx_schedule(dev);
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@ -2685,6 +2705,20 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
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spin_unlock_irqrestore(&np->lock, flags);
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np->link_timeout = jiffies + LINK_TIMEOUT;
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}
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if (events & NVREG_IRQ_RECOVER_ERROR) {
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spin_lock_irq(&np->lock);
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/* disable interrupts on the nic */
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writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
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pci_push(base);
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if (!np->in_shutdown) {
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np->nic_poll_irq |= NVREG_IRQ_OTHER;
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np->recover_error = 1;
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mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
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}
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spin_unlock_irq(&np->lock);
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break;
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}
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if (events & (NVREG_IRQ_UNKNOWN)) {
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printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
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dev->name, events);
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@ -2914,6 +2948,42 @@ static void nv_do_nic_poll(unsigned long data)
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}
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np->nic_poll_irq = 0;
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if (np->recover_error) {
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np->recover_error = 0;
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printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
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if (netif_running(dev)) {
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netif_tx_lock_bh(dev);
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spin_lock(&np->lock);
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/* stop engines */
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nv_stop_rx(dev);
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nv_stop_tx(dev);
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nv_txrx_reset(dev);
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/* drain rx queue */
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nv_drain_rx(dev);
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nv_drain_tx(dev);
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/* reinit driver view of the rx queue */
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set_bufsize(dev);
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if (nv_init_ring(dev)) {
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if (!np->in_shutdown)
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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}
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/* reinit nic view of the rx queue */
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writel(np->rx_buf_sz, base + NvRegOffloadConfig);
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setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
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writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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pci_push(base);
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writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
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pci_push(base);
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/* restart rx engine */
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nv_start_rx(dev);
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nv_start_tx(dev);
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spin_unlock(&np->lock);
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netif_tx_unlock_bh(dev);
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}
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}
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/* FIXME: Do we need synchronize_irq(dev->irq) here? */
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writel(mask, base + NvRegIrqMask);
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