Interrupt chip driver fixes:

- Don't install an hotplug notifier for GICV3-ITS on systems which do not
     need it to prevent a warning in the notifier about inconsistent state
 
   - Add the missing device tree matching for the T-HEAD PLIC variant so the
     related SoC is properly supported.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmIJCMgTHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoaMPD/9phdwtDfMV7pKv3AvKwb3tt5QVkKJ/
 8fcl4QObJcE/1rhoUvWNUyUy/VvcyfVUVZV26jlbMjlIo6W7QIrCr4aV/neps9E3
 bEKsrli/pxtwrZyp5uFGrh0egiO6dFxu3II67GBmbBywkAxhAhc6eFSh5mD2LfB8
 3uJVcle+G1IdKn9ULri5KZtpuqyMIIpkMAGrO/0TdYfiG87rl4cuCkm2PZlreyDC
 llL+61ro6KU9DsSNQ5s7l/qfVsffdKLiPxwkww/IjnP7mWbBb2clMnbh9/YkIE90
 IWNEwqQIS4ACMd9F7IY41qu0u47rEHY/suwFJWC2DccmX7lPRp76qdyjMZbGMN0r
 gt08XA6Utl+d2kQVxG51EQEjOZx9x48lQUTkB2MWQ5PXEMUNk0b4gazkYaI/7bw1
 J7GLoWTaczOOjAhrDGPLChDt0cmBRTzuNz6klRh4KcK3BbMD/Lq9JWMs9QOuNdDl
 o0v5MP+1woie2SlnqFOUIPrthEUdQRTLq0C7vU1FE8iYw74NxHH8Yy5pmfdTDqum
 ZeuIbehog2CtZCJ7GklzcY2tbFu4cXMwWgwdngkcHX80JAb/mWOp6Uz83AFOcIGh
 N/vWJvAwbNq+Y7NbTa2AjB8cPkqFg4DFQpTFsYZNVOuf0ISEl9bR99xQ1+KzOy3+
 NPUClXH+mdKTRA==
 =QWzW
 -----END PGP SIGNATURE-----

Merge tag 'irq-urgent-2022-02-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
 "Interrupt chip driver fixes:

   - Don't install an hotplug notifier for GICV3-ITS on systems which do
     not need it to prevent a warning in the notifier about inconsistent
     state

   - Add the missing device tree matching for the T-HEAD PLIC variant so
     the related SoC is properly supported"

* tag 'irq-urgent-2022-02-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/sifive-plic: Add missing thead,c900-plic match string
  dt-bindings: update riscv plic compatible string
  irqchip/gic-v3-its: Skip HP notifier when no ITS is registered

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
+  T-HEAD PLIC implementation requires setting a delegation bit to allow access
+  from S-mode. So add thead,c900-plic to distinguish them.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -42,12 +46,17 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,fu540-c000-plic
-          - starfive,jh7100-plic
-          - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - enum:
+              - sifive,fu540-c000-plic
+              - starfive,jh7100-plic
+              - canaan,k210-plic
+          - const: sifive,plic-1.0.0
+      - items:
+          - enum:
+              - allwinner,sun20i-d1-plic
+          - const: thead,c900-plic
 
   reg:
     maxItems: 1

drivers/irqchip/irq-gic-v3-its.c

@@ -5517,6 +5517,9 @@ int __init its_lpi_memreserve_init(void)
 	if (!efi_enabled(EFI_CONFIG_TABLES))
 		return 0;
 
+	if (list_empty(&its_nodes))
+		return 0;
+
 	gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
 	state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
 				  "irqchip/arm/gicv3/memreserve:online",

drivers/irqchip/irq-sifive-plic.c

@@ -398,3 +398,4 @@ out_free_priv:
 
 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
+IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */