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arm64: dts: renesas: r8a7795: Fix register mappings on VSPs

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The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Kieran Bingham 2018-02-14 09:55:07 +00:00 committed by Simon Horman
parent d9366032b6
commit c5dcfe6552
1 changed files with 3 additions and 3 deletions
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6
arch/arm64/boot/dts/renesas/r8a7795.dtsi
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@ -2208,7 +2208,7 @@ fcpvi1: fcp@fe9bf000 {
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -2228,7 +2228,7 @@ fcpvd0: fcp@fea27000 {
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x4000>;
reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -2248,7 +2248,7 @@ fcpvd1: fcp@fea2f000 {
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x4000>;
reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;