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net: stmmac: fix rx queue priority assignment

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commit b3da86d432 upstream.

The driver should ensure that same priority is not mapped to multiple
rx queues. From DesignWare Cores Ethernet Quality-of-Service
Databook, section 17.1.29 MAC_RxQ_Ctrl2:
"[...]The software must ensure that the content of this field is
mutually exclusive to the PSRQ fields for other queues, that is,
the same priority is not mapped to multiple Rx queues[...]"

Previously rx_queue_priority() function was:
- clearing all priorities from a queue
- adding new priorities to that queue
After this patch it will:
- first assign new priorities to a queue
- then remove those priorities from all other queues
- keep other priorities previously assigned to that queue

Fixes: a8f5102af2 ("net: stmmac: TX and RX queue priority configuration")
Fixes: 2142754f8b ("net: stmmac: Add MAC related callbacks for XGMAC2")
Signed-off-by: Piotr Wejman <piotrwejman90@gmail.com>
Link: https://lore.kernel.org/r/20240401192239.33942-1-piotrwejman90@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Piotr Wejman 2024-04-01 21:22:39 +02:00 committed by Greg Kroah-Hartman
parent f190a4aa03
commit c5dd42e0c4
2 changed files with 62 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
View file

@ -84,19 +84,41 @@ static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
u32 prio, u32 queue)
{
void __iomem *ioaddr = hw->pcsr;
u32 base_register;
u32 value;
u32 clear_mask = 0;
u32 ctrl2, ctrl3;
int i;
base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
if (queue >= 4)
ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
/* The software must ensure that the same priority
* is not mapped to multiple Rx queues
*/
for (i = 0; i < 4; i++)
clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
GMAC_RXQCTRL_PSRQX_MASK(i));
ctrl2 &= ~clear_mask;
ctrl3 &= ~clear_mask;
/* First assign new priorities to a queue, then
* clear them from others queues
*/
if (queue < 4) {
ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
GMAC_RXQCTRL_PSRQX_MASK(queue);
writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
} else {
queue -= 4;
value = readl(ioaddr + base_register);
value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
GMAC_RXQCTRL_PSRQX_MASK(queue);
writel(value, ioaddr + base_register);
writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
}
}
static void dwmac4_tx_queue_priority(struct mac_device_info *hw,

38
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
View file

@ -103,17 +103,41 @@ static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
u32 queue)
{
void __iomem *ioaddr = hw->pcsr;
u32 value, reg;
u32 clear_mask = 0;
u32 ctrl2, ctrl3;
int i;
reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3;
if (queue >= 4)
ctrl2 = readl(ioaddr + XGMAC_RXQ_CTRL2);
ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3);
/* The software must ensure that the same priority
* is not mapped to multiple Rx queues
*/
for (i = 0; i < 4; i++)
clear_mask |= ((prio << XGMAC_PSRQ_SHIFT(i)) &
XGMAC_PSRQ(i));
ctrl2 &= ~clear_mask;
ctrl3 &= ~clear_mask;
/* First assign new priorities to a queue, then
* clear them from others queues
*/
if (queue < 4) {
ctrl2 |= (prio << XGMAC_PSRQ_SHIFT(queue)) &
XGMAC_PSRQ(queue);
writel(ctrl2, ioaddr + XGMAC_RXQ_CTRL2);
writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3);
} else {
queue -= 4;
value = readl(ioaddr + reg);
value &= ~XGMAC_PSRQ(queue);
value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue);
ctrl3 |= (prio << XGMAC_PSRQ_SHIFT(queue)) &
XGMAC_PSRQ(queue);
writel(value, ioaddr + reg);
writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3);
writel(ctrl2, ioaddr + XGMAC_RXQ_CTRL2);
}
}
static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,