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powerpc/fsl: Force coherent memory on e500mc derivatives
In CoreNet systems it is not allowed to mix M and non-M mappings to the same memory, and coherent DMA accesses are considered to be M mappings for this purpose. Ignoring this has been observed to cause hard lockups in non-SMP kernels on e6500. Furthermore, e6500 implements the LRAT (logical to real address table) which allows KVM guests to control the WIMGE bits. This means that KVM cannot force the M bit on the way it usually does, so the guest had better set it itself. Signed-off-by: Scott Wood <scottwood@freescale.com>
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parent
0d61f0b3e2
commit
c60232029a
4 changed files with 20 additions and 13 deletions
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@ -109,7 +109,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU) || \
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defined(CONFIG_PPC_E500MC)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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#else
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#define _PAGE_BASE (_PAGE_BASE_NC)
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@ -1313,11 +1313,14 @@ skpinv: addi r6,r6,1 /* Increment */
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sync
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isync
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/* The mapping only needs to be cache-coherent on SMP */
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#ifdef CONFIG_SMP
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#define M_IF_SMP MAS2_M
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/*
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* The mapping only needs to be cache-coherent on SMP, except on
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* Freescale e500mc derivatives where it's also needed for coherent DMA.
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*/
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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#define M_IF_NEEDED MAS2_M
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#else
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#define M_IF_SMP 0
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#define M_IF_NEEDED 0
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#endif
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/* 6. Setup KERNELBASE mapping in TLB[0]
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@ -1332,7 +1335,7 @@ skpinv: addi r6,r6,1 /* Increment */
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ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
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mtspr SPRN_MAS1,r6
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LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
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LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED)
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mtspr SPRN_MAS2,r6
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rlwinm r5,r5,0,0,25
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@ -152,11 +152,14 @@ skpinv: addi r6,r6,1 /* Increment */
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tlbivax 0,r9
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TLBSYNC
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/* The mapping only needs to be cache-coherent on SMP */
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#ifdef CONFIG_SMP
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#define M_IF_SMP MAS2_M
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/*
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* The mapping only needs to be cache-coherent on SMP, except on
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* Freescale e500mc derivatives where it's also needed for coherent DMA.
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*/
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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#define M_IF_NEEDED MAS2_M
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#else
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#define M_IF_SMP 0
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#define M_IF_NEEDED 0
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#endif
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#if defined(ENTRY_MAPPING_BOOT_SETUP)
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@ -167,8 +170,8 @@ skpinv: addi r6,r6,1 /* Increment */
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lis r6,(MAS1_VALID|MAS1_IPROT)@h
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ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
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mtspr SPRN_MAS1,r6
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lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
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ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
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lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@h
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ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_NEEDED)@l
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mtspr SPRN_MAS2,r6
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mtspr SPRN_MAS3,r8
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tlbwe
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@ -112,7 +112,7 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
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tsize = __ilog2(size) - 10;
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#ifdef CONFIG_SMP
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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if ((flags & _PAGE_NO_CACHE) == 0)
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flags |= _PAGE_COHERENT;
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#endif
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