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pinctrl: renesas: r8a779g0: Add missing PWM
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed. This patch adds missing PWM settings, and tidies these up. According to Document, GP3_14 Function4 is PWM2_A, but we can't select it at P1SR3[27:24]. This patch just ignore it for now. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto
Geert Uytterhoeven
parent
1c2646b5ce
commit
c606c2fde2
1 changed files with 84 additions and 56 deletions
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@ -310,9 +310,9 @@
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#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -321,7 +321,7 @@
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#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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@ -348,9 +348,9 @@
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#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -375,7 +375,7 @@
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#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -845,15 +845,15 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
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PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
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/* IP2SR1 */
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PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
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@ -875,7 +875,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
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PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
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PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3),
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PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
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PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
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PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
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@ -951,13 +951,14 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
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PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
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PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1),
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PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
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PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
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PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
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PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
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PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
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PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
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PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
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/* IP2SR2 */
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PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
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@ -995,6 +996,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
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PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
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PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
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PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
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PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
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@ -2030,40 +2032,58 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
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PCIE1_CLKREQ_N_MARK,
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};
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/* - PWM0 ------------------------------------------------------------------- */
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static const unsigned int pwm0_pins[] = {
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/* PWM0 */
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/* - PWM0_A ------------------------------------------------------------------- */
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static const unsigned int pwm0_a_pins[] = {
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/* PWM0_A */
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RCAR_GP_PIN(1, 15),
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};
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static const unsigned int pwm0_mux[] = {
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PWM0_MARK,
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static const unsigned int pwm0_a_mux[] = {
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PWM0_A_MARK,
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};
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/* - PWM1 ------------------------------------------------------------------- */
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static const unsigned int pwm1_pins[] = {
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/* PWM1 */
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/* - PWM1_A ------------------------------------------------------------------- */
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static const unsigned int pwm1_a_pins[] = {
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/* PWM1_A */
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RCAR_GP_PIN(3, 13),
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};
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static const unsigned int pwm1_a_mux[] = {
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PWM1_A_MARK,
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};
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/* - PWM1_B ------------------------------------------------------------------- */
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static const unsigned int pwm1_b_pins[] = {
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/* PWM1_B */
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RCAR_GP_PIN(2, 13),
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};
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static const unsigned int pwm1_mux[] = {
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PWM1_MARK,
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static const unsigned int pwm1_b_mux[] = {
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PWM1_B_MARK,
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};
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/* - PWM2 ------------------------------------------------------------------- */
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static const unsigned int pwm2_pins[] = {
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/* PWM2 */
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/* - PWM2_B ------------------------------------------------------------------- */
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static const unsigned int pwm2_b_pins[] = {
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/* PWM2_B */
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RCAR_GP_PIN(2, 14),
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};
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static const unsigned int pwm2_mux[] = {
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PWM2_MARK,
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static const unsigned int pwm2_b_mux[] = {
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PWM2_B_MARK,
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};
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/* - PWM3 ------------------------------------------------------------------- */
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static const unsigned int pwm3_pins[] = {
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/* PWM3 */
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/* - PWM3_A ------------------------------------------------------------------- */
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static const unsigned int pwm3_a_pins[] = {
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/* PWM3_A */
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RCAR_GP_PIN(1, 22),
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};
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static const unsigned int pwm3_mux[] = {
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PWM3_MARK,
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static const unsigned int pwm3_a_mux[] = {
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PWM3_A_MARK,
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};
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/* - PWM3_B ------------------------------------------------------------------- */
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static const unsigned int pwm3_b_pins[] = {
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/* PWM3_B */
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RCAR_GP_PIN(2, 15),
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};
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static const unsigned int pwm3_b_mux[] = {
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PWM3_B_MARK,
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};
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/* - PWM4 ------------------------------------------------------------------- */
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PWM7_MARK,
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};
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/* - PWM8 ------------------------------------------------------------------- */
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static const unsigned int pwm8_pins[] = {
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/* PWM8 */
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/* - PWM8_A ------------------------------------------------------------------- */
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static const unsigned int pwm8_a_pins[] = {
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/* PWM8_A */
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RCAR_GP_PIN(1, 13),
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};
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static const unsigned int pwm8_mux[] = {
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PWM8_MARK,
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static const unsigned int pwm8_a_mux[] = {
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PWM8_A_MARK,
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};
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/* - PWM9 ------------------------------------------------------------------- */
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static const unsigned int pwm9_pins[] = {
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/* PWM9 */
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/* - PWM9_A ------------------------------------------------------------------- */
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static const unsigned int pwm9_a_pins[] = {
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/* PWM9_A */
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RCAR_GP_PIN(1, 14),
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};
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static const unsigned int pwm9_mux[] = {
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PWM9_MARK,
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static const unsigned int pwm9_a_mux[] = {
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PWM9_A_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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@ -2555,16 +2575,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(pcie0_clkreq_n),
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SH_PFC_PIN_GROUP(pcie1_clkreq_n),
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SH_PFC_PIN_GROUP(pwm0),
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SH_PFC_PIN_GROUP(pwm1),
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SH_PFC_PIN_GROUP(pwm2),
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SH_PFC_PIN_GROUP(pwm3),
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SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(pwm1_a),
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SH_PFC_PIN_GROUP(pwm1_b),
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SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
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SH_PFC_PIN_GROUP(pwm3_a),
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SH_PFC_PIN_GROUP(pwm3_b),
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SH_PFC_PIN_GROUP(pwm4),
|
||||
SH_PFC_PIN_GROUP(pwm5),
|
||||
SH_PFC_PIN_GROUP(pwm6),
|
||||
SH_PFC_PIN_GROUP(pwm7),
|
||||
SH_PFC_PIN_GROUP(pwm8),
|
||||
SH_PFC_PIN_GROUP(pwm9),
|
||||
SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
|
||||
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
|
|
@ -2812,19 +2834,23 @@ static const char * const pcie_groups[] = {
|
|||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"pwm0",
|
||||
/* suffix might be updated */
|
||||
"pwm0_a",
|
||||
};
|
||||
|
||||
static const char * const pwm1_groups[] = {
|
||||
"pwm1",
|
||||
"pwm1_a",
|
||||
"pwm1_b",
|
||||
};
|
||||
|
||||
static const char * const pwm2_groups[] = {
|
||||
"pwm2",
|
||||
/* suffix might be updated */
|
||||
"pwm2_b",
|
||||
};
|
||||
|
||||
static const char * const pwm3_groups[] = {
|
||||
"pwm3",
|
||||
"pwm3_a",
|
||||
"pwm3_b",
|
||||
};
|
||||
|
||||
static const char * const pwm4_groups[] = {
|
||||
|
|
@ -2844,11 +2870,13 @@ static const char * const pwm7_groups[] = {
|
|||
};
|
||||
|
||||
static const char * const pwm8_groups[] = {
|
||||
"pwm8",
|
||||
/* suffix might be updated */
|
||||
"pwm8_a",
|
||||
};
|
||||
|
||||
static const char * const pwm9_groups[] = {
|
||||
"pwm9",
|
||||
/* suffix might be updated */
|
||||
"pwm9_a",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
|
|
|
|||
Loading…
Reference in a new issue