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clk: tegra: Implement locking for super clock
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not actually used by the code. Fixed with this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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1 changed files with 15 additions and 3 deletions
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@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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{
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{
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struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
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struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
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u32 val, state;
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u32 val, state;
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int err = 0;
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u8 parent_index, shift;
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u8 parent_index, shift;
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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val = readl_relaxed(mux->reg);
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val = readl_relaxed(mux->reg);
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state = val & SUPER_STATE_MASK;
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state = val & SUPER_STATE_MASK;
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@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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(index == mux->pllx_index))) {
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(index == mux->pllx_index))) {
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parent_index = clk_super_get_parent(hw);
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parent_index = clk_super_get_parent(hw);
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if ((parent_index == mux->div2_index) ||
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if ((parent_index == mux->div2_index) ||
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(parent_index == mux->pllx_index))
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(parent_index == mux->pllx_index)) {
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return -EINVAL;
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err = -EINVAL;
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goto out;
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}
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val ^= SUPER_LP_DIV2_BYPASS;
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val ^= SUPER_LP_DIV2_BYPASS;
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writel_relaxed(val, mux->reg);
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writel_relaxed(val, mux->reg);
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@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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writel_relaxed(val, mux->reg);
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writel_relaxed(val, mux->reg);
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udelay(2);
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udelay(2);
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return 0;
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out:
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return err;
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}
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}
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const struct clk_ops tegra_clk_super_ops = {
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const struct clk_ops tegra_clk_super_ops = {
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