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ARM: mmp: support DT in timer
Parse timer from DTS file. Avoid to use hardcoding marco for register. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
c24b31147a
commit
c68ef2b592
1 changed files with 60 additions and 21 deletions
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@ -25,6 +25,9 @@
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/sched_clock.h>
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#include <mach/addr-map.h>
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@ -41,6 +44,8 @@
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#define MAX_DELTA (0xfffffffe)
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#define MIN_DELTA (16)
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static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
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/*
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* FIXME: the timer needs some delay to stablize the counter capture
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*/
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@ -48,12 +53,12 @@ static inline uint32_t timer_read(void)
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{
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int delay = 100;
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__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
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__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
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while (delay--)
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cpu_relax();
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return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
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return __raw_readl(mmp_timer_base + TMR_CVWR(1));
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}
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static u32 notrace mmp_read_sched_clock(void)
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@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
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/*
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* Clear pending interrupt status.
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*/
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__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
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__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
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__raw_writel(0x02, mmp_timer_base + TMR_CER);
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c->event_handler(c);
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@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta,
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
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__raw_writel(0x02, mmp_timer_base + TMR_CER);
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/*
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* Clear and enable timer match 0 interrupt.
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*/
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__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
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__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
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__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
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__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
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/*
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* Setup new clockevent timer value.
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*/
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__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
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__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
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/*
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* Enable timer 0.
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*/
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__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
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__raw_writel(0x03, mmp_timer_base + TMR_CER);
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local_irq_restore(flags);
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@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode,
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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/* disable the matching interrupt */
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__raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
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__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
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break;
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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@ -157,27 +162,27 @@ static struct clocksource cksrc = {
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static void __init timer_config(void)
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{
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uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
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uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
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__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
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ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
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__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
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__raw_writel(ccr, mmp_timer_base + TMR_CCR);
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/* set timer 0 to periodic mode, and timer 1 to free-running mode */
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__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
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__raw_writel(0x2, mmp_timer_base + TMR_CMR);
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__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
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__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
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__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
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__raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
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__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
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__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
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__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
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__raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
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__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
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/* enable timer 1 counter */
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__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
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__raw_writel(0x2, mmp_timer_base + TMR_CER);
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}
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static struct irqaction timer_irq = {
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@ -203,3 +208,37 @@ void __init timer_init(int irq)
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clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
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clockevents_register_device(&ckevt);
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}
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#ifdef CONFIG_OF
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static struct of_device_id mmp_timer_dt_ids[] = {
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{ .compatible = "mrvl,mmp-timer", },
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{}
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};
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void __init mmp_dt_init_timer(void)
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{
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struct device_node *np;
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int irq, ret;
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np = of_find_matching_node(NULL, mmp_timer_dt_ids);
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if (!np) {
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ret = -ENODEV;
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goto out;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -EINVAL;
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goto out;
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}
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mmp_timer_base = of_iomap(np, 0);
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if (!mmp_timer_base) {
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ret = -ENOMEM;
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goto out;
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}
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timer_init(irq);
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return;
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out:
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pr_err("Failed to get timer from device tree with error:%d\n", ret);
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}
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#endif
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