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pinctrl: renesas: rzg2l: Add RZ/G3S support
Add basic support for RZ/G3S to be able to boot from SD card, have a running console port, and use GPIOs. RZ/G3S has 82 general-purpose IO ports. Support for the remaining pin functions (e.g. Ethernet, XSPI) will be added along with controller-specific support. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-22-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea
Geert Uytterhoeven
parent
60e4dc192c
commit
c6a088e5a0
1 changed files with 124 additions and 2 deletions
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@ -58,13 +58,19 @@
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#define PIN_CFG_IOLH_C BIT(13)
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#define PIN_CFG_SOFT_PS BIT(14)
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#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
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PIN_CFG_SR | \
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#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
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(PIN_CFG_IOLH_##group | \
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PIN_CFG_PUPD | \
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PIN_CFG_FILONOFF | \
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PIN_CFG_FILNUM | \
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PIN_CFG_FILCLKSEL)
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#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
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PIN_CFG_SR)
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#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
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PIN_CFG_SOFT_PS)
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#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
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PIN_CFG_FILONOFF | \
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PIN_CFG_FILNUM | \
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@ -1314,6 +1320,36 @@ static const u32 r9a07g043_gpio_configs[] = {
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RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
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};
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static const u32 r9a08g045_gpio_configs[] = {
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RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
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RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH0)), /* P1 */
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RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH0)), /* P2 */
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RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH0)), /* P3 */
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RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH0)), /* P4 */
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RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
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RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
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RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH1)), /* P7 */
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RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH1)), /* P8 */
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RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH1)), /* P9 */
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RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
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PIN_CFG_IO_VMC_ETH1)), /* P10 */
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RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
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RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
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RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
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RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
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RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
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RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
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RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
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RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
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};
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static const struct {
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struct rzg2l_dedicated_configs common[35];
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struct rzg2l_dedicated_configs rzg2l_pins[7];
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@ -1400,6 +1436,46 @@ static const struct {
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}
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};
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static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
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{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
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PIN_CFG_FILCLKSEL)) },
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{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
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PIN_CFG_SOFT_PS)) },
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{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
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{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
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{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD0)) },
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{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
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{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD1)) },
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{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD1)) },
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{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD1)) },
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{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD1)) },
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{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
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PIN_CFG_IO_VMC_SD1)) },
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};
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static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
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{
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unsigned int gpioint;
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@ -1761,6 +1837,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
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BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
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ARRAY_SIZE(rzg2l_gpio_names));
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BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
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ARRAY_SIZE(rzg2l_gpio_names));
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pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
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if (!pctrl)
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return -ENOMEM;
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@ -1806,6 +1885,35 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
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.iolh_groupb_oi = { 100, 66, 50, 33, },
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};
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static const struct rzg2l_hwcfg rzg3s_hwcfg = {
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.regs = {
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.pwpr = 0x3000,
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.sd_ch = 0x3004,
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},
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.iolh_groupa_ua = {
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/* 1v8 power source */
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[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
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/* 3v3 power source */
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[RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
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},
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.iolh_groupb_ua = {
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/* 1v8 power source */
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[RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
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/* 3v3 power source */
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[RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
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},
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.iolh_groupc_ua = {
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/* 1v8 power source */
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[RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
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/* 2v5 source */
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[RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
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/* 3v3 power source */
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[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
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},
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.drive_strength_ua = true,
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.func_base = 1,
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};
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static struct rzg2l_pinctrl_data r9a07g043_data = {
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.port_pins = rzg2l_gpio_names,
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.port_pin_configs = r9a07g043_gpio_configs,
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@ -1827,6 +1935,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
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.hwcfg = &rzg2l_hwcfg,
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};
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static struct rzg2l_pinctrl_data r9a08g045_data = {
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.port_pins = rzg2l_gpio_names,
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.port_pin_configs = r9a08g045_gpio_configs,
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.n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
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.dedicated_pins = rzg3s_dedicated_pins,
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.n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
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.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
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.hwcfg = &rzg3s_hwcfg,
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};
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static const struct of_device_id rzg2l_pinctrl_of_table[] = {
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{
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.compatible = "renesas,r9a07g043-pinctrl",
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@ -1836,6 +1954,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
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.compatible = "renesas,r9a07g044-pinctrl",
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.data = &r9a07g044_data,
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},
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{
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.compatible = "renesas,r9a08g045-pinctrl",
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.data = &r9a08g045_data,
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},
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{ /* sentinel */ }
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};
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