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gve: Update GVE documentation to describe DQO
DQO is a new descriptor format for our next generation virtual NIC. Signed-off-by: Bailey Forrest <bcf@google.com> Reviewed-by: Willem de Bruijn <willemb@google.com> Reviewed-by: Catherine Sullivan <csully@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -47,13 +47,24 @@ The driver interacts with the device in the following ways:
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- Transmit and Receive Queues
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- Transmit and Receive Queues
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- See description below
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- See description below
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Descriptor Formats
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------------------
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GVE supports two descriptor formats: GQI and DQO. These two formats have
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entirely different descriptors, which will be described below.
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Registers
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Registers
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---------
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---------
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All registers are MMIO and big endian.
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All registers are MMIO.
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The registers are used for initializing and configuring the device as well as
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The registers are used for initializing and configuring the device as well as
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querying device status in response to management interrupts.
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querying device status in response to management interrupts.
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Endianness
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----------
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- Admin Queue messages and registers are all Big Endian.
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- GQI descriptors and datapath registers are Big Endian.
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- DQO descriptors and datapath registers are Little Endian.
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Admin Queue (AQ)
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Admin Queue (AQ)
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----------------
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----------------
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The Admin Queue is a PAGE_SIZE memory block, treated as an array of AQ
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The Admin Queue is a PAGE_SIZE memory block, treated as an array of AQ
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@ -97,10 +108,10 @@ the queues associated with that interrupt.
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The handler for these irqs schedule the napi for that block to run
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The handler for these irqs schedule the napi for that block to run
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and poll the queues.
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and poll the queues.
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Traffic Queues
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GQI Traffic Queues
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--------------
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------------------
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gVNIC's queues are composed of a descriptor ring and a buffer and are
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GQI queues are composed of a descriptor ring and a buffer and are assigned to a
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assigned to a notification block.
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notification block.
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The descriptor rings are power-of-two-sized ring buffers consisting of
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The descriptor rings are power-of-two-sized ring buffers consisting of
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fixed-size descriptors. They advance their head pointer using a __be32
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fixed-size descriptors. They advance their head pointer using a __be32
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@ -121,3 +132,35 @@ Receive
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The buffers for receive rings are put into a data ring that is the same
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The buffers for receive rings are put into a data ring that is the same
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length as the descriptor ring and the head and tail pointers advance over
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length as the descriptor ring and the head and tail pointers advance over
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the rings together.
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the rings together.
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DQO Traffic Queues
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------------------
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- Every TX and RX queue is assigned a notification block.
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- TX and RX buffers queues, which send descriptors to the device, use MMIO
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doorbells to notify the device of new descriptors.
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- RX and TX completion queues, which receive descriptors from the device, use a
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"generation bit" to know when a descriptor was populated by the device. The
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driver initializes all bits with the "current generation". The device will
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populate received descriptors with the "next generation" which is inverted
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from the current generation. When the ring wraps, the current/next generation
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are swapped.
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- It's the driver's responsibility to ensure that the RX and TX completion
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queues are not overrun. This can be accomplished by limiting the number of
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descriptors posted to HW.
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- TX packets have a 16 bit completion_tag and RX buffers have a 16 bit
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buffer_id. These will be returned on the TX completion and RX queues
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respectively to let the driver know which packet/buffer was completed.
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Transmit
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~~~~~~~~
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A packet's buffers are DMA mapped for the device to access before transmission.
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After the packet was successfully transmitted, the buffers are unmapped.
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Receive
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~~~~~~~
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The driver posts fixed sized buffers to HW on the RX buffer queue. The packet
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received on the associated RX queue may span multiple descriptors.
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