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[POWERPC] Handle alignment faults on new FP load/store instructions
This adds code to handle alignment traps generated by the following new floating-point load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): lfiwax load floating-point as integer word algebraic indexed stfiwx store floating-point as integer word indexed lfdp load floating-point double pair lfdpx load floating-point double pair indexed stfdp store floating-point double pair stfdpx store floating-point double pair indexed All these except stfiwx are new in POWER6. lfdp/lfdpx/stfdp/stfdpx load and store 16 bytes of memory into an even/odd FP register pair. In little-endian mode each 8-byte value is byte-reversed separately (i.e. not as a 16-byte unit). lfiwax/stfiwx load or store the lower 4 bytes of a floating-point register from/to memory; lfiwax sets the upper 4 bytes of the FP register to the sign extension of the value loaded. Signed-off-by: Paul Mackerras <paulus@samba.org>
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09a54101e1
commit
c6d4267ece
1 changed files with 49 additions and 8 deletions
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@ -38,7 +38,7 @@ struct aligninfo {
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/* Bits in the flags field */
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#define LD 0 /* load */
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#define ST 1 /* store */
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#define SE 2 /* sign-extend value */
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#define SE 2 /* sign-extend value, or FP ld/st as word */
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#define F 4 /* to/from fp regs */
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#define U 8 /* update index register */
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#define M 0x10 /* multiple load/store */
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@ -87,9 +87,9 @@ static struct aligninfo aligninfo[128] = {
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{ 8, LD+F+U }, /* 00 1 1001: lfdu */
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{ 4, ST+F+S+U }, /* 00 1 1010: stfsu */
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{ 8, ST+F+U }, /* 00 1 1011: stfdu */
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INVALID, /* 00 1 1100 */
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{ 16, LD+F }, /* 00 1 1100: lfdp */
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INVALID, /* 00 1 1101 */
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INVALID, /* 00 1 1110 */
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{ 16, ST+F }, /* 00 1 1110: stfdp */
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INVALID, /* 00 1 1111 */
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{ 8, LD }, /* 01 0 0000: ldx */
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INVALID, /* 01 0 0001 */
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@ -167,10 +167,10 @@ static struct aligninfo aligninfo[128] = {
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{ 8, LD+F }, /* 11 0 1001: lfdx */
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{ 4, ST+F+S }, /* 11 0 1010: stfsx */
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{ 8, ST+F }, /* 11 0 1011: stfdx */
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INVALID, /* 11 0 1100 */
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{ 8, LD+M }, /* 11 0 1101: lmd */
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INVALID, /* 11 0 1110 */
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{ 8, ST+M }, /* 11 0 1111: stmd */
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{ 16, LD+F }, /* 11 0 1100: lfdpx */
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{ 4, LD+F+SE }, /* 11 0 1101: lfiwax */
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{ 16, ST+F }, /* 11 0 1110: stfdpx */
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{ 4, ST+F }, /* 11 0 1111: stfiwx */
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{ 4, LD+U }, /* 11 1 0000: lwzux */
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INVALID, /* 11 1 0001 */
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{ 4, ST+U }, /* 11 1 0010: stwux */
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@ -356,6 +356,42 @@ static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
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return 1;
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}
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/*
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* Emulate floating-point pair loads and stores.
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* Only POWER6 has these instructions, and it does true little-endian,
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* so we don't need the address swizzling.
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*/
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static int emulate_fp_pair(struct pt_regs *regs, unsigned char __user *addr,
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unsigned int reg, unsigned int flags)
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{
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char *ptr = (char *) ¤t->thread.fpr[reg];
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int i, ret;
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if (!(flags & F))
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return 0;
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if (reg & 1)
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return 0; /* invalid form: FRS/FRT must be even */
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if (!(flags & SW)) {
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/* not byte-swapped - easy */
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if (!(flags & ST))
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ret = __copy_from_user(ptr, addr, 16);
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else
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ret = __copy_to_user(addr, ptr, 16);
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} else {
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/* each FPR value is byte-swapped separately */
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ret = 0;
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for (i = 0; i < 16; ++i) {
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if (!(flags & ST))
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ret |= __get_user(ptr[i^7], addr + i);
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else
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ret |= __put_user(ptr[i^7], addr + i);
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}
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}
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if (ret)
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return -EFAULT;
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return 1; /* exception handled and fixed up */
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}
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/*
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* Called on alignment exception. Attempts to fixup
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@ -471,6 +507,10 @@ int fix_alignment(struct pt_regs *regs)
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flush_fp_to_thread(current);
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}
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/* Special case for 16-byte FP loads and stores */
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if (nb == 16)
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return emulate_fp_pair(regs, addr, reg, flags);
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/* If we are loading, get the data from user space, else
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* get it from register values
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*/
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@ -531,7 +571,8 @@ int fix_alignment(struct pt_regs *regs)
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* or floating point single precision conversion
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*/
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switch (flags & ~(U|SW)) {
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case LD+SE: /* sign extend */
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case LD+SE: /* sign extending integer loads */
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case LD+F+SE: /* sign extend for lfiwax */
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if ( nb == 2 )
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data.ll = data.x16.low16;
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else /* nb must be 4 */
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