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drm/i915/gt: Convert the leftover for_each_engine(gt)
Use the local gt for iterating over the available set of engines. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191018115331.8980-1-chris@chris-wilson.co.uk
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bcce7d90d1
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c6e07ada8e
4 changed files with 11 additions and 11 deletions
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@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
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set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
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set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
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for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
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for_each_engine(engine, rc6_to_gt(rc6), id)
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set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
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@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
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set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
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set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
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for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
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for_each_engine(engine, rc6_to_gt(rc6), id)
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set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
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@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
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set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
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set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
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set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
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for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
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for_each_engine(engine, rc6_to_gt(rc6), id)
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set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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set(uncore, GEN6_RC_SLEEP, 0);
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set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
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@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
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set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
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set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
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for_each_engine(engine, i915, id)
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for_each_engine(engine, rc6_to_gt(rc6), id)
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set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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set(uncore, GEN6_RC_SLEEP, 0);
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@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
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set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
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set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
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for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
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for_each_engine(engine, rc6_to_gt(rc6), id)
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set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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set(uncore, GEN6_RC_SLEEP, 0);
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@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
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set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
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set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
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for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
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for_each_engine(engine, rc6_to_gt(rc6), id)
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set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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set(uncore, GEN6_RC6_THRESHOLD, 0x557);
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@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
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struct intel_engine_cs *signaller;
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*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
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for_each_engine(signaller, i915, id) {
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for_each_engine(signaller, engine->gt, id) {
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if (signaller == engine)
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continue;
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@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
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i915_reg_t last_reg = {}; /* keep gcc quiet */
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*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
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for_each_engine(signaller, i915, id) {
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for_each_engine(signaller, engine->gt, id) {
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if (signaller == engine)
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continue;
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@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
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/* Insert a delay before the next switch! */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(last_reg);
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*cs++ = intel_gt_scratch_offset(rq->engine->gt,
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*cs++ = intel_gt_scratch_offset(engine->gt,
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INTEL_GT_SCRATCH_FIELD_DEFAULT);
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*cs++ = MI_NOOP;
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}
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@ -1569,7 +1569,7 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
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}
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intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
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for_each_engine(engine, i915, id) {
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for_each_engine(engine, gt, id) {
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/* GFX_MODE is per-ring on gen7+ */
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ENGINE_WRITE(engine,
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RING_MODE_GEN7,
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@ -301,7 +301,7 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
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if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
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return;
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for_each_engine(engine, i915, id) {
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for_each_engine(engine, gt, id) {
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struct intel_engine_pmu *pmu = &engine->pmu;
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unsigned long flags;
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bool busy;
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