drm/amdgpu: Initialize dce_virtual_ip_funcs
For virtual display feature, first need to initialize dce_virtual_ip_funcs, which will be used when set ip blocks. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Emily Deng
Alex Deucher
parent
16925c92db
commit
c6e14f40ba
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@ -58,7 +58,8 @@ amdgpu-y += \
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# add DCE block
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amdgpu-y += \
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dce_v10_0.o \
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dce_v11_0.o
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dce_v11_0.o \
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dce_virtual.o
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# add GFX block
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amdgpu-y += \
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@ -335,7 +335,7 @@ int amdgpu_crtc_set_config(struct drm_mode_set *set)
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return ret;
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}
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static const char *encoder_names[38] = {
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static const char *encoder_names[41] = {
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"NONE",
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"INTERNAL_LVDS",
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"INTERNAL_TMDS1",
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@ -374,6 +374,9 @@ static const char *encoder_names[38] = {
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"TRAVIS",
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"INTERNAL_VCE",
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"INTERNAL_UNIPHY3",
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"HDMI_ANX9805",
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"INTERNAL_AMCLK",
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"VIRTUAL",
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};
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static const char *hpd_names[6] = {
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@ -0,0 +1,308 @@
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "amdgpu.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_i2c.h"
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#include "atom.h"
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#include "amdgpu_atombios.h"
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#include "atombios_crtc.h"
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#include "atombios_encoders.h"
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#include "amdgpu_pll.h"
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#include "amdgpu_connectors.h"
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static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
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static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
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static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
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.cursor_set2 = NULL,
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.cursor_move = NULL,
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.gamma_set = NULL,
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.set_config = NULL,
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.destroy = NULL,
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.page_flip = NULL,
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};
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static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
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.dpms = NULL,
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.mode_fixup = NULL,
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.mode_set = NULL,
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.mode_set_base = NULL,
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.mode_set_base_atomic = NULL,
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.prepare = NULL,
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.commit = NULL,
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.load_lut = NULL,
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.disable = NULL,
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};
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static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
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{
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struct amdgpu_crtc *amdgpu_crtc;
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int i;
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amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
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(AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
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if (amdgpu_crtc == NULL)
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return -ENOMEM;
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drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
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drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
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amdgpu_crtc->crtc_id = index;
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adev->mode_info.crtcs[index] = amdgpu_crtc;
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for (i = 0; i < 256; i++) {
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amdgpu_crtc->lut_r[i] = i << 2;
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amdgpu_crtc->lut_g[i] = i << 2;
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amdgpu_crtc->lut_b[i] = i << 2;
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}
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amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
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amdgpu_crtc->encoder = NULL;
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amdgpu_crtc->connector = NULL;
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drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
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return 0;
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}
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static int dce_virtual_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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dce_virtual_set_display_funcs(adev);
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dce_virtual_set_irq_funcs(adev);
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adev->mode_info.num_crtc = 1;
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adev->mode_info.num_hpd = 1;
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adev->mode_info.num_dig = 1;
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return 0;
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}
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static bool dce_virtual_get_connector_info(struct amdgpu_device *adev)
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{
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struct amdgpu_i2c_bus_rec ddc_bus;
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struct amdgpu_router router;
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struct amdgpu_hpd hpd;
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/* look up gpio for ddc, hpd */
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ddc_bus.valid = false;
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hpd.hpd = AMDGPU_HPD_NONE;
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/* needed for aux chan transactions */
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ddc_bus.hpd = hpd.hpd;
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memset(&router, 0, sizeof(router));
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router.ddc_valid = false;
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router.cd_valid = false;
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amdgpu_display_add_connector(adev,
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0,
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ATOM_DEVICE_CRT1_SUPPORT,
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DRM_MODE_CONNECTOR_VIRTUAL, &ddc_bus,
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CONNECTOR_OBJECT_ID_VIRTUAL,
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&hpd,
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&router);
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amdgpu_display_add_encoder(adev, ENCODER_VIRTUAL_ENUM_VIRTUAL,
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ATOM_DEVICE_CRT1_SUPPORT,
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0);
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amdgpu_link_encoder_connector(adev->ddev);
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return true;
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}
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static int dce_virtual_sw_init(void *handle)
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{
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int r, i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_irq_add_id(adev, 229, &adev->crtc_irq);
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if (r)
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return r;
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adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
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adev->ddev->mode_config.max_width = 16384;
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adev->ddev->mode_config.max_height = 16384;
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adev->ddev->mode_config.preferred_depth = 24;
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adev->ddev->mode_config.prefer_shadow = 1;
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adev->ddev->mode_config.fb_base = adev->mc.aper_base;
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r = amdgpu_modeset_create_props(adev);
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if (r)
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return r;
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adev->ddev->mode_config.max_width = 16384;
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adev->ddev->mode_config.max_height = 16384;
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/* allocate crtcs */
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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r = dce_virtual_crtc_init(adev, i);
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if (r)
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return r;
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}
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dce_virtual_get_connector_info(adev);
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amdgpu_print_display_setup(adev->ddev);
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drm_kms_helper_poll_init(adev->ddev);
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adev->mode_info.mode_config_initialized = true;
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return 0;
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}
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static int dce_virtual_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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kfree(adev->mode_info.bios_hardcoded_edid);
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drm_kms_helper_poll_fini(adev->ddev);
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drm_mode_config_cleanup(adev->ddev);
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adev->mode_info.mode_config_initialized = false;
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return 0;
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}
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static int dce_virtual_hw_init(void *handle)
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{
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return 0;
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}
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static int dce_virtual_hw_fini(void *handle)
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{
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return 0;
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}
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static int dce_virtual_suspend(void *handle)
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{
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return dce_virtual_hw_fini(handle);
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}
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static int dce_virtual_resume(void *handle)
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{
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int ret;
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ret = dce_virtual_hw_init(handle);
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return ret;
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}
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static bool dce_virtual_is_idle(void *handle)
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{
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return true;
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}
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static int dce_virtual_wait_for_idle(void *handle)
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{
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return 0;
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}
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static int dce_virtual_soft_reset(void *handle)
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{
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return 0;
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}
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static int dce_virtual_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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return 0;
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}
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static int dce_virtual_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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return 0;
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}
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const struct amd_ip_funcs dce_virtual_ip_funcs = {
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.name = "dce_virtual",
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.early_init = dce_virtual_early_init,
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.late_init = NULL,
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.sw_init = dce_virtual_sw_init,
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.sw_fini = dce_virtual_sw_fini,
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.hw_init = dce_virtual_hw_init,
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.hw_fini = dce_virtual_hw_fini,
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.suspend = dce_virtual_suspend,
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.resume = dce_virtual_resume,
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.is_idle = dce_virtual_is_idle,
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.wait_for_idle = dce_virtual_wait_for_idle,
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.soft_reset = dce_virtual_soft_reset,
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.set_clockgating_state = dce_virtual_set_clockgating_state,
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.set_powergating_state = dce_virtual_set_powergating_state,
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};
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static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
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.set_vga_render_state = NULL,
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.bandwidth_update = NULL,
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.vblank_get_counter = NULL,
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.vblank_wait = NULL,
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.is_display_hung = NULL,
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.backlight_set_level = NULL,
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.backlight_get_level = NULL,
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.hpd_sense = NULL,
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.hpd_set_polarity = NULL,
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.hpd_get_gpio_reg = NULL,
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.page_flip = NULL,
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.page_flip_get_scanoutpos = NULL,
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.add_encoder = NULL,
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.add_connector = &amdgpu_connector_add,
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.stop_mc_access = NULL,
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.resume_mc_access = NULL,
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};
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static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
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{
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if (adev->mode_info.funcs == NULL)
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adev->mode_info.funcs = &dce_virtual_display_funcs;
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}
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static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
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.set = NULL,
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.process = NULL,
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};
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static const struct amdgpu_irq_src_funcs dce_virtual_pageflip_irq_funcs = {
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.set = NULL,
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.process = NULL,
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};
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static const struct amdgpu_irq_src_funcs dce_virtual_hpd_irq_funcs = {
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.set = NULL,
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.process = NULL,
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};
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static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
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adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
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adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
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adev->pageflip_irq.funcs = &dce_virtual_pageflip_irq_funcs;
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adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
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adev->hpd_irq.funcs = &dce_virtual_hpd_irq_funcs;
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}
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@ -0,0 +1,29 @@
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __DCE_VIRTUAL_H__
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#define __DCE_VIRTUAL_H__
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extern const struct amd_ip_funcs dce_virtual_ip_funcs;
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#endif
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