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drm/i915/ehl: Introduce Mule Creek Canyon PCH
Although EHL introduces a new PCH, the South Display part of the PCH that we care about is nearly identical to ICP, just with some pins remapped. Most notably, Port C is mapped to the pins that ICP uses for TC Port 1. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190615004210.16656-1-matthew.d.roper@intel.com
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32a1963148
commit
c6f7acb80a
7 changed files with 74 additions and 10 deletions
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@ -1348,12 +1348,21 @@ static const u8 icp_ddc_pin_map[] = {
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[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
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};
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static const u8 mcc_ddc_pin_map[] = {
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[MCC_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
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[MCC_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
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[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
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};
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static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
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{
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const u8 *ddc_pin_map;
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int n_entries;
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if (HAS_PCH_ICP(dev_priv)) {
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if (HAS_PCH_MCC(dev_priv)) {
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ddc_pin_map = mcc_ddc_pin_map;
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n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
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} else if (HAS_PCH_ICP(dev_priv)) {
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ddc_pin_map = icp_ddc_pin_map;
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n_entries = ARRAY_SIZE(icp_ddc_pin_map);
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} else if (HAS_PCH_CNP(dev_priv)) {
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@ -88,11 +88,19 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
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[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
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};
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static const struct gmbus_pin gmbus_pins_mcc[] = {
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[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
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[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
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};
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/* pin is expected to be valid */
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static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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if (HAS_PCH_ICP(dev_priv))
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if (HAS_PCH_MCC(dev_priv))
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return &gmbus_pins_mcc[pin];
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else if (HAS_PCH_ICP(dev_priv))
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return &gmbus_pins_icp[pin];
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else if (HAS_PCH_CNP(dev_priv))
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return &gmbus_pins_cnp[pin];
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@ -111,7 +119,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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{
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unsigned int size;
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if (HAS_PCH_ICP(dev_priv))
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if (HAS_PCH_MCC(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_mcc);
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else if (HAS_PCH_ICP(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_icp);
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else if (HAS_PCH_CNP(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_cnp);
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@ -2959,6 +2959,28 @@ static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
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return ddc_pin;
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}
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static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
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{
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u8 ddc_pin;
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switch (port) {
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case PORT_A:
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ddc_pin = GMBUS_PIN_1_BXT;
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break;
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case PORT_B:
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ddc_pin = GMBUS_PIN_2_BXT;
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break;
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case PORT_C:
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ddc_pin = GMBUS_PIN_9_TC1_ICP;
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break;
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default:
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MISSING_CASE(port);
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ddc_pin = GMBUS_PIN_1_BXT;
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break;
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}
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return ddc_pin;
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}
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static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
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enum port port)
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{
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@ -2995,7 +3017,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
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return info->alternate_ddc_pin;
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}
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if (HAS_PCH_ICP(dev_priv))
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if (HAS_PCH_MCC(dev_priv))
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ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
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else if (HAS_PCH_ICP(dev_priv))
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ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
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else if (HAS_PCH_CNP(dev_priv))
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ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
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@ -314,6 +314,9 @@ enum vbt_gmbus_ddi {
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ICL_DDC_BUS_PORT_2,
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ICL_DDC_BUS_PORT_3,
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ICL_DDC_BUS_PORT_4,
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MCC_DDC_BUS_DDI_A = 0x1,
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MCC_DDC_BUS_DDI_B,
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MCC_DDC_BUS_DDI_C = 0x4,
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};
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#define DP_AUX_A 0x40
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@ -218,6 +218,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
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DRM_DEBUG_KMS("Found Ice Lake PCH\n");
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WARN_ON(!IS_ICELAKE(dev_priv));
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return PCH_ICP;
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case INTEL_PCH_MCC_DEVICE_ID_TYPE:
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DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
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WARN_ON(!IS_ELKHARTLAKE(dev_priv));
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return PCH_MCC;
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default:
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return PCH_NONE;
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}
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@ -245,7 +249,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
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* make an educated guess as to which PCH is really there.
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*/
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if (IS_ICELAKE(dev_priv))
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if (IS_ELKHARTLAKE(dev_priv))
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id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
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else if (IS_ICELAKE(dev_priv))
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id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
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else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
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id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
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@ -534,6 +534,7 @@ enum intel_pch {
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PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
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PCH_CNP, /* Cannon/Comet Lake PCH */
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PCH_ICP, /* Ice Lake PCH */
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PCH_MCC, /* Mule Creek Canyon PCH */
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};
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#define QUIRK_LVDS_SSC_DISABLE (1<<1)
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@ -2356,12 +2357,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
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#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
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#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
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#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
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#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
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#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
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#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
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#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
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#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
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#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
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@ -142,6 +142,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
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[HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
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};
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static const u32 hpd_mcc[HPD_NUM_PINS] = {
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[HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
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[HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
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[HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
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};
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static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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i915_reg_t iir, i915_reg_t ier)
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{
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@ -2498,7 +2504,8 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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cpt_serr_int_handler(dev_priv);
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}
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static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
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const u32 *pins)
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{
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u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
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u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
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@ -2512,7 +2519,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
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ddi_hotplug_trigger,
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dig_hotplug_reg, hpd_icp,
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dig_hotplug_reg, pins,
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icp_ddi_port_hotplug_long_detect);
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}
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@ -2524,7 +2531,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
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tc_hotplug_trigger,
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dig_hotplug_reg, hpd_icp,
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dig_hotplug_reg, pins,
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icp_tc_port_hotplug_long_detect);
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}
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@ -2955,8 +2962,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
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I915_WRITE(SDEIIR, iir);
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ret = IRQ_HANDLED;
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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icp_irq_handler(dev_priv, iir);
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
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icp_irq_handler(dev_priv, iir, hpd_mcc);
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else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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icp_irq_handler(dev_priv, iir, hpd_icp);
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else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
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spt_irq_handler(dev_priv, iir);
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else
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