drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution
Update the maximum resolution reported for HEVC encoding on VCN 3 devices to reflect its 8K encoding capability. v2: Also update the max height for H.264 encoding to match spec. (Ruijing) Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -98,6 +98,16 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode =
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};
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/* Sienna Cichlid */
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static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
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};
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static const struct amdgpu_video_codecs sc_video_codecs_encode = {
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.codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
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.codec_array = sc_video_codecs_encode_array,
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};
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static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
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{
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
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@ -136,8 +146,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =
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/* SRIOV Sienna Cichlid, not const since data is controlled by host */
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static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
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{
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
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};
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static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
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@ -237,12 +247,12 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
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} else {
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if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
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if (encode)
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*codecs = &nv_video_codecs_encode;
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*codecs = &sc_video_codecs_encode;
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else
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*codecs = &sc_video_codecs_decode_vcn1;
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} else {
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if (encode)
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*codecs = &nv_video_codecs_encode;
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*codecs = &sc_video_codecs_encode;
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else
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*codecs = &sc_video_codecs_decode_vcn0;
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}
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@ -251,14 +261,14 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
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case IP_VERSION(3, 0, 16):
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case IP_VERSION(3, 0, 2):
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if (encode)
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*codecs = &nv_video_codecs_encode;
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*codecs = &sc_video_codecs_encode;
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else
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*codecs = &sc_video_codecs_decode_vcn0;
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return 0;
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case IP_VERSION(3, 1, 1):
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case IP_VERSION(3, 1, 2):
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if (encode)
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*codecs = &nv_video_codecs_encode;
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*codecs = &sc_video_codecs_encode;
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else
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*codecs = &yc_video_codecs_decode;
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return 0;
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