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[ARM] 4392/2: Do not corrupt the SP register in compressed/head.S
ARMv7 support code requires a valid stack for saving/restoring registers as the whole D-cache flushing function is more complex. This patch ensures that the SP register is not corrupted. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1 changed files with 4 additions and 1 deletions
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@ -247,7 +247,7 @@ not_relocated: mov r0, #0
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mov r3, r7
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bl decompress_kernel
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add r0, r0, #127
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add r0, r0, #127 + 128 @ alignment + stack
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bic r0, r0, #127 @ align the kernel length
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/*
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* r0 = decompressed kernel length
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@ -269,6 +269,7 @@ not_relocated: mov r0, #0
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stmia r1!, {r9 - r14}
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cmp r2, r3
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blo 1b
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add sp, r1, #128 @ relocate the stack
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bl cache_clean_flush
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add pc, r5, r0 @ call relocation code
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@ -476,6 +477,7 @@ __common_mmu_cache_on:
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*/
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.align 5
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reloc_start: add r9, r5, r0
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sub r9, r9, #128 @ do not copy the stack
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debug_reloc_start
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mov r1, r4
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1:
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@ -486,6 +488,7 @@ reloc_start: add r9, r5, r0
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cmp r5, r9
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blo 1b
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add sp, r1, #128 @ relocate the stack
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debug_reloc_end
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call_kernel: bl cache_clean_flush
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