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drm/amd/pp: Add struct profile_mode_setting for smu7
Move configurable profiling parameters to struct profile_mode_setting and initialize current_profile_setting. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
527d9427fa
commit
c7429b3ae9
7 changed files with 56 additions and 39 deletions
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@ -1484,8 +1484,6 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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data->dll_default_on = false;
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data->mclk_dpm0_activity_target = 0xa;
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data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT;
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data->sclk_activity_target = SMU7_SCLK_TARGETACTIVITY_DFLT;
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data->vddc_vddgfx_delta = 300;
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data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
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data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
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@ -1509,6 +1507,14 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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data->enable_pkg_pwr_tracking_feature = true;
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data->force_pcie_gen = PP_PCIEGenInvalid;
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data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
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data->current_profile_setting.bupdate_sclk = 1;
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data->current_profile_setting.sclk_up_hyst = 0;
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data->current_profile_setting.sclk_down_hyst = 100;
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data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
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data->current_profile_setting.bupdate_sclk = 1;
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data->current_profile_setting.mclk_up_hyst = 0;
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data->current_profile_setting.mclk_down_hyst = 100;
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data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
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if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
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uint8_t tmp1, tmp2;
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@ -186,6 +186,17 @@ struct smu7_odn_dpm_table {
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uint32_t odn_mclk_min_limit;
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};
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struct profile_mode_setting {
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uint8_t bupdate_sclk;
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uint8_t sclk_up_hyst;
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uint8_t sclk_down_hyst;
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uint16_t sclk_activity;
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uint8_t bupdate_mclk;
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uint8_t mclk_up_hyst;
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uint8_t mclk_down_hyst;
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uint16_t mclk_activity;
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};
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struct smu7_hwmgr {
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struct smu7_dpm_table dpm_table;
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struct smu7_dpm_table golden_dpm_table;
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@ -289,8 +300,6 @@ struct smu7_hwmgr {
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struct smu7_pcie_perf_range pcie_lane_power_saving;
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bool use_pcie_performance_levels;
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bool use_pcie_power_saving_levels;
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uint16_t mclk_activity_target;
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uint16_t sclk_activity_target;
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uint32_t mclk_dpm0_activity_target;
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uint32_t low_sclk_interrupt_threshold;
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uint32_t last_mclk_dpm_enable_mask;
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@ -316,6 +325,8 @@ struct smu7_hwmgr {
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uint16_t mem_latency_high;
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uint16_t mem_latency_low;
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uint32_t vr_config;
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struct profile_mode_setting custom_profile_setting;
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struct profile_mode_setting current_profile_setting;
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};
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/* To convert to Q8.8 format for firmware */
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@ -444,8 +444,8 @@ static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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level->EnabledForActivity = 0;
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/* this level can be used for throttling.*/
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level->EnabledForThrottle = 1;
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level->UpH = 0;
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level->DownH = 0;
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level->UpH = data->current_profile_setting.sclk_up_hyst;
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level->DownH = data->current_profile_setting.sclk_down_hyst;
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level->VoltageDownH = 0;
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level->PowerThrottle = 0;
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@ -492,7 +492,7 @@ static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = ci_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->sclk_activity_target,
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data->current_profile_setting.sclk_activity,
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&levels[i]);
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if (result)
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return result;
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@ -1226,12 +1226,12 @@ static int ci_populate_single_memory_level(
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memory_level->EnabledForThrottle = 1;
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memory_level->EnabledForActivity = 1;
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memory_level->UpH = 0;
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memory_level->DownH = 100;
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memory_level->UpH = data->current_profile_setting.mclk_up_hyst;
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memory_level->DownH = data->current_profile_setting.mclk_down_hyst;
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memory_level->VoltageDownH = 0;
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/* Indicates maximum activity level for this performance level.*/
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memory_level->ActivityLevel = data->mclk_activity_target;
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memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
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memory_level->StutterEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->EdcReadEnable = 0;
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@ -1515,7 +1515,7 @@ static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownH = 100;
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table->MemoryACPILevel.VoltageDownH = 0;
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/* Indicates maximum activity level for this performance level.*/
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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@ -1001,8 +1001,8 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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level->CcPwrDynRm1 = 0;
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level->EnabledForActivity = 0;
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level->EnabledForThrottle = 1;
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level->UpHyst = 10;
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level->DownHyst = 0;
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level->UpHyst = data->current_profile_setting.sclk_up_hyst;
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level->DownHyst = data->current_profile_setting.sclk_down_hyst;
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level->VoltageDownHyst = 0;
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level->PowerThrottle = 0;
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@ -1059,7 +1059,7 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = fiji_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->sclk_activity_target,
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data->current_profile_setting.sclk_activity,
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&levels[i]);
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if (result)
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return result;
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@ -1222,10 +1222,10 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
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mem_level->EnabledForThrottle = 1;
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mem_level->EnabledForActivity = 0;
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mem_level->UpHyst = 0;
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mem_level->DownHyst = 100;
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mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
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mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
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mem_level->VoltageDownHyst = 0;
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mem_level->ActivityLevel = data->mclk_activity_target;
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mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
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mem_level->StutterEnable = false;
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mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
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@ -1443,7 +1443,7 @@ static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.ActivityLevel =
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PP_HOST_TO_SMC_US(data->mclk_activity_target);
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PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
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table->MemoryACPILevel.StutterEnable = false;
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
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@ -928,8 +928,8 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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graphic_level->EnabledForActivity = 0;
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/* this level can be used for throttling.*/
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graphic_level->EnabledForThrottle = 1;
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graphic_level->UpHyst = 0;
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graphic_level->DownHyst = 100;
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graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst;
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graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst;
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graphic_level->VoltageDownHyst = 0;
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graphic_level->PowerThrottle = 0;
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@ -985,7 +985,7 @@ static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = iceland_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->sclk_activity_target,
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data->current_profile_setting.sclk_activity,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result != 0)
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return result;
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@ -1271,12 +1271,12 @@ static int iceland_populate_single_memory_level(
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memory_level->EnabledForThrottle = 1;
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memory_level->EnabledForActivity = 0;
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memory_level->UpHyst = 0;
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memory_level->DownHyst = 100;
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memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
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memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
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memory_level->VoltageDownHyst = 0;
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/* Indicates maximum activity level for this performance level.*/
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memory_level->ActivityLevel = data->mclk_activity_target;
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memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
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memory_level->StutterEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->EdcReadEnable = 0;
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@ -1557,7 +1557,7 @@ static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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/* Indicates maximum activity level for this performance level.*/
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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@ -968,8 +968,8 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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level->CcPwrDynRm1 = 0;
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level->EnabledForActivity = 0;
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level->EnabledForThrottle = 1;
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level->UpHyst = 10;
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level->DownHyst = 0;
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level->UpHyst = data->current_profile_setting.sclk_up_hyst;
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level->DownHyst = data->current_profile_setting.sclk_down_hyst;
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level->VoltageDownHyst = 0;
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level->PowerThrottle = 0;
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data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
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@ -1033,7 +1033,7 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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result = polaris10_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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hw_data->sclk_activity_target,
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hw_data->current_profile_setting.sclk_activity,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result)
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return result;
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@ -1130,10 +1130,10 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
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mem_level->MclkFrequency = clock;
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mem_level->EnabledForThrottle = 1;
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mem_level->EnabledForActivity = 0;
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mem_level->UpHyst = 0;
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mem_level->DownHyst = 100;
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mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
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mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
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mem_level->VoltageDownHyst = 0;
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mem_level->ActivityLevel = data->mclk_activity_target;
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mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
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mem_level->StutterEnable = false;
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mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
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@ -1314,7 +1314,7 @@ static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.ActivityLevel =
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PP_HOST_TO_SMC_US(data->mclk_activity_target);
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PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
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@ -644,8 +644,8 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
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graphic_level->EnabledForActivity = 0;
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/* this level can be used for throttling.*/
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graphic_level->EnabledForThrottle = 1;
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graphic_level->UpHyst = 0;
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graphic_level->DownHyst = 0;
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graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst;
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graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst;
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graphic_level->VoltageDownHyst = 0;
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graphic_level->PowerThrottle = 0;
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@ -704,7 +704,7 @@ static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = tonga_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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data->sclk_activity_target,
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data->current_profile_setting.sclk_activity,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result != 0)
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return result;
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@ -994,12 +994,12 @@ static int tonga_populate_single_memory_level(
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memory_level->EnabledForThrottle = 1;
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memory_level->EnabledForActivity = 0;
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memory_level->UpHyst = 0;
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memory_level->DownHyst = 100;
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memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
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memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
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memory_level->VoltageDownHyst = 0;
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/* Indicates maximum activity level for this performance level.*/
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memory_level->ActivityLevel = data->mclk_activity_target;
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memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
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memory_level->StutterEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->EdcReadEnable = 0;
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@ -1289,7 +1289,7 @@ static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.VoltageDownHyst = 0;
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/* Indicates maximum activity level for this performance level.*/
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table->MemoryACPILevel.ActivityLevel =
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PP_HOST_TO_SMC_US(data->mclk_activity_target);
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PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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