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mtd: spi-nor: move all micron-st specifics into micron-st.c
The flag status register is only available on micron flashes. Move all the functions around that into the micron module. This is almost a mechanical move except for the spi_nor_fsr_ready() which now also checks the normal status register. Previously, this was done in spi_nor_ready(). Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-25-michael@walle.cc
This commit is contained in:
Michael Walle
Tudor Ambarus
parent
56b852e863
commit
c770abe52d
3 changed files with 135 additions and 130 deletions
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@ -412,50 +412,6 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
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return ret;
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}
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/**
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* spi_nor_read_fsr() - Read the Flag Status Register.
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* @nor: pointer to 'struct spi_nor'
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* @fsr: pointer to a DMA-able buffer where the value of the
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* Flag Status Register will be written. Should be at least 2
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* bytes.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(1, fsr, 0));
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if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
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op.addr.nbytes = nor->params->rdsr_addr_nbytes;
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op.dummy.nbytes = nor->params->rdsr_dummy;
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/*
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* We don't want to read only one byte in DTR mode. So,
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* read 2 and then discard the second byte.
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*/
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op.data.nbytes = 2;
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}
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
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1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d reading FSR\n", ret);
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return ret;
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}
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/**
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* spi_nor_read_cr() - Read the Configuration Register using the
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* SPINOR_OP_RDCR (35h) command.
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@ -664,75 +620,6 @@ int spi_nor_sr_ready(struct spi_nor *nor)
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return !(nor->bouncebuf[0] & SR_WIP);
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}
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/**
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* spi_nor_clear_fsr() - Clear the Flag Status Register.
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* @nor: pointer to 'struct spi_nor'.
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*/
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static void spi_nor_clear_fsr(struct spi_nor *nor)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
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NULL, 0);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
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}
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/**
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* spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
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* ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 1 if ready, 0 if not ready, -errno on errors.
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*/
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static int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
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if (nor->bouncebuf[0] & FSR_E_ERR)
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dev_err(nor->dev, "Erase operation failed.\n");
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else
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dev_err(nor->dev, "Program operation failed.\n");
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if (nor->bouncebuf[0] & FSR_PT_ERR)
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dev_err(nor->dev,
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"Attempted to modify a protected sector.\n");
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spi_nor_clear_fsr(nor);
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/*
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* WEL bit remains set to one when an erase or page program
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* error occurs. Issue a Write Disable command to protect
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* against inadvertent writes that can possibly corrupt the
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* contents of the memory.
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*/
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ret = spi_nor_write_disable(nor);
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if (ret)
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return ret;
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return -EIO;
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}
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return !!(nor->bouncebuf[0] & FSR_READY);
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}
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/**
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* spi_nor_ready() - Query the flash to see if it is ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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@ -741,19 +628,11 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
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*/
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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/* Flashes might override the standard routine. */
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if (nor->params->ready)
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return nor->params->ready(nor);
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sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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if (fsr < 0)
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return fsr;
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return sr && fsr;
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return spi_nor_sr_ready(nor);
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}
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/**
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@ -8,6 +8,8 @@
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#include "core.h"
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
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#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
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#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
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#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
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@ -17,6 +19,12 @@
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#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
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#define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
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/* Flag Status Register bits */
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#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
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#define FSR_E_ERR BIT(5) /* Erase operation status */
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#define FSR_P_ERR BIT(4) /* Program operation status */
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#define FSR_PT_ERR BIT(1) /* Protection error bit */
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static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
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{
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struct spi_mem_op op;
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@ -273,6 +281,125 @@ static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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return spi_nor_write_disable(nor);
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}
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/**
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* spi_nor_read_fsr() - Read the Flag Status Register.
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* @nor: pointer to 'struct spi_nor'
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* @fsr: pointer to a DMA-able buffer where the value of the
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* Flag Status Register will be written. Should be at least 2
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* bytes.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(1, fsr, 0));
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if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
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op.addr.nbytes = nor->params->rdsr_addr_nbytes;
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op.dummy.nbytes = nor->params->rdsr_dummy;
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/*
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* We don't want to read only one byte in DTR mode. So,
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* read 2 and then discard the second byte.
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*/
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op.data.nbytes = 2;
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}
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
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1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d reading FSR\n", ret);
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return ret;
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}
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/**
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* spi_nor_clear_fsr() - Clear the Flag Status Register.
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* @nor: pointer to 'struct spi_nor'.
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*/
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static void spi_nor_clear_fsr(struct spi_nor *nor)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
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NULL, 0);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
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}
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/**
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* spi_nor_fsr_ready() - Query the Status Register as well as the Flag Status
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* Register to see if the flash is ready for new commands. If there are any
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* errors in the FSR clear them.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 1 if ready, 0 if not ready, -errno on errors.
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*/
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static int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int sr_ready, ret;
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sr_ready = spi_nor_sr_ready(nor);
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if (sr_ready < 0)
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return sr_ready;
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ret = spi_nor_read_fsr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
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if (nor->bouncebuf[0] & FSR_E_ERR)
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dev_err(nor->dev, "Erase operation failed.\n");
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else
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dev_err(nor->dev, "Program operation failed.\n");
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if (nor->bouncebuf[0] & FSR_PT_ERR)
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dev_err(nor->dev,
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"Attempted to modify a protected sector.\n");
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spi_nor_clear_fsr(nor);
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/*
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* WEL bit remains set to one when an erase or page program
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* error occurs. Issue a Write Disable command to protect
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* against inadvertent writes that can possibly corrupt the
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* contents of the memory.
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*/
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ret = spi_nor_write_disable(nor);
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if (ret)
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return ret;
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return -EIO;
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}
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return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
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}
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static void micron_st_nor_default_init(struct spi_nor *nor)
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{
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nor->flags |= SNOR_F_HAS_LOCK;
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@ -281,8 +408,15 @@ static void micron_st_nor_default_init(struct spi_nor *nor)
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nor->params->set_4byte_addr_mode = micron_st_nor_set_4byte_addr_mode;
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}
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static void micron_st_nor_late_init(struct spi_nor *nor)
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{
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if (nor->flags & SNOR_F_USE_FSR)
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nor->params->ready = spi_nor_fsr_ready;
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}
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static const struct spi_nor_fixups micron_st_nor_fixups = {
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.default_init = micron_st_nor_default_init,
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.late_init = micron_st_nor_late_init,
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};
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const struct spi_nor_manufacturer spi_nor_micron = {
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@ -47,8 +47,6 @@
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#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
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#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
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#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
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#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
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#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
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#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
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@ -126,12 +124,6 @@
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/* Enhanced Volatile Configuration Register bits */
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#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
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/* Flag Status Register bits */
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#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
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#define FSR_E_ERR BIT(5) /* Erase operation status */
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#define FSR_P_ERR BIT(4) /* Program operation status */
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#define FSR_PT_ERR BIT(1) /* Protection error bit */
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/* Status Register 2 bits. */
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#define SR2_QUAD_EN_BIT1 BIT(1)
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#define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
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