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This is the bulk of pin control changes for the v5.15 kernel cycle, 

no core changes at all this time, just driver work!
 
 New drivers:
 
 - New subdriver for Intel Keem Bay (an ARM-based SoC)
 
 - New subdriver for Qualcomm MDM9607 and SM6115
 
 - New subdriver for ST Microelectronics STM32MP135
 
 - New subdriver for Freescale i.MX8ULP ("Ultra Low Power")
 
 - New subdriver for Ingenic X2100
 
 - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO
 
 - Support Samsung Exynos850
 
 - Support Renesas RZ/G2L
 
 Enhancements:
 
 - A major refactoring of the Rockchip driver, breaking part of it out
   to a separate GPIO driver in drivers/gpio
 
 - Pin bias support on Renesas r8a77995
 
 - Add SCI pins support to Ingenic JZ4755 and JZ4760
 
 - Mediatek device tree bindings converted to YAML
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Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.15 kernel cycle, no
  core changes at all this time, just driver work!

  New drivers:

   - New subdriver for Intel Keem Bay (an ARM-based SoC)

   - New subdriver for Qualcomm MDM9607 and SM6115

   - New subdriver for ST Microelectronics STM32MP135

   - New subdriver for Freescale i.MX8ULP ("Ultra Low Power")

   - New subdriver for Ingenic X2100

   - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO

   - Support Samsung Exynos850

   - Support Renesas RZ/G2L

  Enhancements:

   - A major refactoring of the Rockchip driver, breaking part of it out
     to a separate GPIO driver in drivers/gpio

   - Pin bias support on Renesas r8a77995

   - Add SCI pins support to Ingenic JZ4755 and JZ4760

   - Mediatek device tree bindings converted to YAML"

* tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits)
  pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
  pinctrl: samsung: Add Exynos850 SoC specific data
  dt-bindings: pinctrl: samsung: Add Exynos850 doc
  MAINTAINERS: Add maintainers for amd-pinctrl driver
  pinctrl: Add Intel Keem Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver
  pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device
  dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property
  dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML
  dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments
  dt-bindings: mediatek: convert pinctrl to yaml
  arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl
  arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl
  pinctrl: ingenic: Add .max_register in regmap_config
  pinctrl: ingenic: Fix bias config for X2000(E)
  pinctrl: ingenic: Fix incorrect pull up/down info
  pinctrl: Ingenic: Add pinctrl driver for X2100.
  dt-bindings: pinctrl: Add bindings for Ingenic X2100.
  pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760.
  pinctrl: Ingenic: Improve the code.
  ...
This commit is contained in:
Linus Torvalds 2021-09-02 14:22:56 -07:00
parent 75d6e7d9ce 0485335295
commit c793011242
67 changed files with 10136 additions and 1442 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml Normal file
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@ -0,0 +1,79 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX8ULP IOMUX Controller
maintainers:
- Jacky Bai <ping.bai@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
const: fsl,imx8ulp-iomuxc1
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 5 integers and represents the mux and config
setting for one pin. The first 4 integers <mux_config_reg input_reg
mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_config_reg" indicates the offset of mux register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_mode" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
iomuxc: pinctrl@298c0000 {
compatible = "fsl,imx8ulp-iomuxc1";
reg = <0x298c0000 0x10000>;
pinctrl_lpuart5: lpuart5grp {
fsl,pins =
<0x0138 0x08F0 0x4 0x3 0x3>,
<0x013C 0x08EC 0x4 0x3 0x3>;
};
};
...

10
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
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@ -19,10 +19,10 @@ description: >
pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.
The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
PA to PG, for a total of 224 pins.
pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains
6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO
ports, PA to PG, for a total of 224 pins.
maintainers:
- Paul Cercueil <paul@crapouillou.net>
@ -47,6 +47,7 @@ properties:
- ingenic,x1500-pinctrl
- ingenic,x1830-pinctrl
- ingenic,x2000-pinctrl
- ingenic,x2100-pinctrl
- items:
- const: ingenic,jz4760b-pinctrl
- const: ingenic,jz4760-pinctrl
@ -85,6 +86,7 @@ patternProperties:
- ingenic,x1500-gpio
- ingenic,x1830-gpio
- ingenic,x2000-gpio
- ingenic,x2100-gpio
reg:
items:

135
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml Normal file
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@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay pin controller Device Tree Bindings
maintainers:
- Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
description: |
Intel Keem Bay SoC integrates a pin controller which enables control
of pin directions, input/output values and configuration
for a total of 80 pins.
properties:
compatible:
const: intel,keembay-pinctrl
reg:
maxItems: 2
gpio-controller: true
'#gpio-cells':
const: 2
ngpios:
description: The number of GPIOs exposed.
const: 80
interrupts:
description:
Specifies the interrupt lines to be used by the controller.
Each interrupt line is shared by upto 4 GPIO lines.
maxItems: 8
interrupt-controller: true
'#interrupt-cells':
const: 2
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
description:
Child nodes can be specified to contain pin configuration information,
which can then be utilized by pinctrl client devices.
The following properties are supported.
properties:
pins:
description: |
The name(s) of the pins to be configured in the child node.
Supported pin names are "GPIO0" up to "GPIO79".
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
description: IO pads drive strength in milli Ampere.
enum: [2, 4, 8, 12]
bias-bus-hold:
type: boolean
input-schmitt-enable:
type: boolean
slew-rate:
description: GPIO slew rate control.
0 - Fast(~100MHz)
1 - Slow(~50MHz)
enum: [0, 1]
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- ngpios
- '#gpio-cells'
- interrupts
- interrupt-controller
- '#interrupt-cells'
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
// Example 1
gpio@0 {
compatible = "intel,keembay-pinctrl";
reg = <0x600b0000 0x88>,
<0x600b0190 0x1ac>;
gpio-controller;
ngpios = <0x50>;
#gpio-cells = <0x2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
};
// Example 2
gpio@1 {
compatible = "intel,keembay-pinctrl";
reg = <0x600c0000 0x88>,
<0x600c0190 0x1ac>;
gpio-controller;
ngpios = <0x50>;
#gpio-cells = <0x2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
};

8
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
View File

@ -43,19 +43,19 @@ group emmc_nb
group pwm0
- pin 11 (GPIO1-11)
- functions pwm, gpio
- functions pwm, led, gpio
group pwm1
- pin 12
- functions pwm, gpio
- functions pwm, led, gpio
group pwm2
- pin 13
- functions pwm, gpio
- functions pwm, led, gpio
group pwm3
- pin 14
- functions pwm, gpio
- functions pwm, led, gpio
group pmic1
- pin 7

206
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml Normal file
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@ -0,0 +1,206 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT65xx Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
enum:
- mediatek,mt2701-pinctrl
- mediatek,mt2712-pinctrl
- mediatek,mt6397-pinctrl
- mediatek,mt7623-pinctrl
- mediatek,mt8127-pinctrl
- mediatek,mt8135-pinctrl
- mediatek,mt8167-pinctrl
- mediatek,mt8173-pinctrl
- mediatek,mt8516-pinctrl
reg:
maxItems: 1
pins-are-numbered:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Specify the subnodes are using numbered pinmux to specify pins.
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
mediatek,pctl-regmap:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
description: |
Should be phandles of the syscfg node.
interrupt-controller: true
interrupts:
minItems: 1
maxItems: 3
"#interrupt-cells":
const: 2
required:
- compatible
- pins-are-numbered
- gpio-controller
- "#gpio-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up:
description: |
Besides generic pinconfig options, it can be used as the pull up
settings for 2 pull resistors, R0 and R1. User can configure those
special pins. Some macros have been defined for this usage, such
as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
valid arguments.
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
description: |
Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8135-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0-0 {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
i2c2_pins_a: i2c2-0 {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3-0 {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
};
};
};
};

173
Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml Normal file
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@ -0,0 +1,173 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT6797 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT6797 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6797-pinctrl
reg:
minItems: 5
maxItems: 5
reg-names:
items:
- const: gpio
- const: iocfgl
- const: iocfgb
- const: iocfgr
- const: iocfgt
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- reg-names
- gpio-controller
- "#gpio-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-enable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 8, 12, 16]
slew-rate:
enum: [0, 1]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart_pins_a: uart-0 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
};

373
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT7622 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT7622 Pin controller is used to control SoC pins.
properties:
compatible:
enum:
- mediatek,mt7622-pinctrl
- mediatek,mt7629-pinctrl
reg:
maxItems: 1
reg-names:
items:
- const: eint
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
if:
required:
- interrupt-controller
then:
required:
- reg-names
- interrupts
- "#interrupt-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'mux':
type: object
additionalProperties: false
description: |
pinmux configuration nodes.
$ref: "/schemas/pinctrl/pinmux-node.yaml"
properties:
function:
description: |
A string containing the name of the function to mux to the group.
enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, sd,
spi, tdm, uart, watchdog, wifi]
groups:
description: |
An array of strings. Each string contains the name of a group.
drive-strength:
enum: [4, 8, 12, 16]
required:
- groups
- function
allOf:
- if:
properties:
function:
const: emmc
then:
properties:
groups:
enum: [emmc, emmc_rst]
- if:
properties:
function:
const: eth
then:
properties:
groups:
enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw,
rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio]
- if:
properties:
function:
const: i2c
then:
properties:
groups:
enum: [i2c0, i2c_0, i2c_1, i2c1_0, i2c1_1, i2c1_2, i2c2_0,
i2c2_1, i2c2_2]
- if:
properties:
function:
const: i2s
then:
properties:
groups:
enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data,
i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws,
i2s1_out_data, i2s2_out_data, i2s3_out_data,
i2s4_out_data]
- if:
properties:
function:
const: ir
then:
properties:
groups:
enum: [ir_0_tx, ir_1_tx, ir_2_tx, ir_0_rx, ir_1_rx, ir_2_rx]
- if:
properties:
function:
const: led
then:
properties:
groups:
enum: [ephy_leds, ephy0_led, ephy1_led, ephy2_led, ephy3_led,
ephy4_led, wled, wf2g_led, wf5g_led]
- if:
properties:
function:
const: flash
then:
properties:
groups:
enum: [par_nand, snfi, spi_nor]
- if:
properties:
function:
const: pcie
then:
properties:
groups:
enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken,
pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq,
pcie0_pad_perst, pcie1_pad_perst, pcie_pereset,
pcie_wake, pcie_clkreq]
- if:
properties:
function:
const: pmic
then:
properties:
groups:
enum: [pmic_bus]
- if:
properties:
function:
const: pwm
then:
properties:
groups:
enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1,
pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0,
pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1,
pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3,
pwm_ch7_0, pwm_0, pwm_1]
- if:
properties:
function:
const: sd
then:
properties:
groups:
enum: [sd_0, sd_1]
- if:
properties:
function:
const: spi
then:
properties:
groups:
enum: [spic0_0, spic0_1, spic1_0, spic1_1, spic2_0_wp_hold,
spic2_0, spi_0, spi_1, spi_wp, spi_hold]
- if:
properties:
function:
const: tdm
then:
properties:
groups:
enum: [tdm_0_out_mclk_bclk_ws, tdm_0_in_mclk_bclk_ws,
tdm_0_out_data, tdm_0_in_data, tdm_1_out_mclk_bclk_ws,
tdm_1_in_mclk_bclk_ws, tdm_1_out_data, tdm_1_in_data]
- if:
properties:
function:
const: uart
then:
properties:
groups:
enum: [uart0_0_tx_rx, uart1_0_tx_rx, uart1_0_rts_cts,
uart1_1_tx_rx, uart1_1_rts_cts, uart2_0_tx_rx,
uart2_0_rts_cts, uart2_1_tx_rx, uart2_1_rts_cts,
uart2_2_tx_rx, uart2_2_rts_cts, uart2_3_tx_rx,
uart3_0_tx_rx, uart3_1_tx_rx, uart3_1_rts_cts,
uart4_0_tx_rx, uart4_1_tx_rx, uart4_1_rts_cts,
uart4_2_tx_rx, uart4_2_rts_cts, uart0_txd_rxd,
uart1_0_txd_rxd, uart1_0_cts_rts, uart1_1_txd_rxd,
uart1_1_cts_rts, uart2_0_txd_rxd, uart2_0_cts_rts,
uart2_1_txd_rxd, uart2_1_cts_rts]
- if:
properties:
function:
const: watchdog
then:
properties:
groups:
enum: [watchdog]
- if:
properties:
function:
const: wifi
then:
properties:
groups:
enum: [wf0_2g, wf0_5g]
'conf':
type: object
additionalProperties: false
description: |
pinconf configuration nodes.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
groups:
description: |
An array of strings. Each string contains the name of a group.
Valid values are the same as the pinmux node.
pins:
description: |
An array of strings. Each string contains the name of a pin.
enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0,
RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS,
I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT,
I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,
G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2,
G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6,
NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0,
MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1,
MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2,
MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3,
MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL,
PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS,
GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N,
PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2,
AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4,
PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA,
WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4,
WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG,
EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS,
EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N,
WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD,
UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD,
UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N,
PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5,
GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK,
TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3,
WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6]
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-enable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [4, 8, 12, 16]
slew-rate:
enum: [0, 1]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pins
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10211000 {
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
pinctrl_eth_default: eth-0 {
mux-mdio {
groups = "mdc_mdio";
function = "eth";
drive-strength = <12>;
};
mux-gmac2 {
groups = "rgmii_via_gmac2";
function = "eth";
drive-strength = <12>;
};
mux-esw {
groups = "esw";
function = "eth";
drive-strength = <8>;
};
conf-mdio {
pins = "MDC";
bias-pull-up;
};
};
};
};

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@ -0,0 +1,228 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8183 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT8183 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8183-pinctrl
reg:
minItems: 10
maxItems: 10
reg-names:
items:
- const: iocfg0
- const: iocfg1
- const: iocfg2
- const: iocfg3
- const: iocfg4
- const: iocfg5
- const: iocfg6
- const: iocfg7
- const: iocfg8
- const: eint
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
gpio-ranges:
minItems: 1
maxItems: 5
description: |
GPIO valid number range.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- gpio-ranges
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c-0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c-1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
};
};

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@ -1,156 +0,0 @@
* Mediatek MT65XX Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
"mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
Eg: <&pio 6 0>
<[phandle of the gpio controller node]
[line number within the gpio controller]
[flags]>
Values for gpio specifier:
- Line number: is a value between 0 to 202.
- Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
Only the following flags are supported:
0 - GPIO_ACTIVE_HIGH
1 - GPIO_ACTIVE_LOW
Optional properties:
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
- reg: physicall address base for EINT registers
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
So when config bias-pull-up, it support arguments for those special pins.
Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
See dt-bindings/pinctrl/mt65xx.h.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
Examples:
#include "mt8135-pinfunc.h"
...
{
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0@0 {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1@0 {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <55>;
};
};
i2c2_pins_a: i2c2@0 {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3@0 {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <55>;
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <55>;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
};
};
...
}
};

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* MediaTek MT6797 Pin Controller
The MediaTek's MT6797 Pin controller is used to control SoC pins.
Required properties:
- compatible: Value should be one of the following.
"mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
- reg: Should contain address and size for gpio, iocfgl, iocfgb,
iocfgr and iocfgt register bases.
- reg-names: An array of strings describing the "reg" entries. Must
contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
Optional properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
input-schmitt-disable, output-enable output-low, output-high,
drive-strength, and slew-rate are valid.
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
'1' for slower slew rate respectively. Valid arguments for 'drive-strength'
is limited, such as 2, 4, 8, 12, or 16 in mA.
Some optional vendor properties as defined are valid to specify in a
pinconf subnode:
- mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
- mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
- mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
or 3 for the advanced pull-up resistors.
- mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
or 3 for the advanced pull-down resistors.
Examples:
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart1_pins_a: uart1 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};

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== MediaTek MT7622 pinctrl controller ==
Required properties for the root node:
- compatible: Should be one of the following
"mediatek,mt7622-pinctrl" for MT7622 SoC
"mediatek,mt7629-pinctrl" for MT7629 SoC
- reg: offset and length of the pinctrl space
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the pin number and the
second is the GPIO flags.
Optional properties:
- interrupt-controller : Marks the device node as an interrupt controller
If the property interrupt-controller is defined, following property is required
- reg-names: A string describing the "reg" entries. Must contain "eint".
- interrupts : The interrupt output from the controller.
- #interrupt-cells: Should be two.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
MT7622 pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
We support 2 types of configuration nodes. Those nodes can be either pinmux
nodes or pinconf nodes. Each configuration node can consist of multiple nodes
describing the pinmux and pinconf options.
The name of each subnode doesn't matter as long as it is unique; all subnodes
should be enumerated and processed purely based on their content.
== pinmux nodes content ==
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
Required properties are:
- groups: An array of strings. Each string contains the name of a group.
Valid values for these names are listed below.
- function: A string containing the name of the function to mux to the
group. Valid values for function names are listed below.
== pinconf nodes content ==
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
Required properties are:
- pins: An array of strings. Each string contains the name of a pin.
Valid values for these names are listed below.
- groups: An array of strings. Each string contains the name of a group.
Valid values for these names are listed below.
Optional properies are:
bias-disable, bias-pull, bias-pull-down, input-enable,
input-schmitt-enable, input-schmitt-disable, output-enable
output-low, output-high, drive-strength, slew-rate
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
slower slew rate respectively.
Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
The following specific properties as defined are valid to specify in a pinconf
subnode:
Optional properties are:
- mediatek,tdsel: An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments are from 0
to 15.
- mediatek,rdsel: An integer describing the steps for input level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments are from 0
to 63.
== Valid values for pins, function and groups on MT7622 ==
Valid values for pins are:
pins can be referenced via the pin names as the below table shown and the
related physical number is also put ahead of those names which helps cross
references to pins between groups to know whether pins assignment conflict
happens among devices try to acquire those available pins.
Pin #: Valid values for pins
-----------------------------
PIN 0: "GPIO_A"
PIN 1: "I2S1_IN"
PIN 2: "I2S1_OUT"
PIN 3: "I2S_BCLK"
PIN 4: "I2S_WS"
PIN 5: "I2S_MCLK"
PIN 6: "TXD0"
PIN 7: "RXD0"
PIN 8: "SPI_WP"
PIN 9: "SPI_HOLD"
PIN 10: "SPI_CLK"
PIN 11: "SPI_MOSI"
PIN 12: "SPI_MISO"
PIN 13: "SPI_CS"
PIN 14: "I2C_SDA"
PIN 15: "I2C_SCL"
PIN 16: "I2S2_IN"
PIN 17: "I2S3_IN"
PIN 18: "I2S4_IN"
PIN 19: "I2S2_OUT"
PIN 20: "I2S3_OUT"
PIN 21: "I2S4_OUT"
PIN 22: "GPIO_B"
PIN 23: "MDC"
PIN 24: "MDIO"
PIN 25: "G2_TXD0"
PIN 26: "G2_TXD1"
PIN 27: "G2_TXD2"
PIN 28: "G2_TXD3"
PIN 29: "G2_TXEN"
PIN 30: "G2_TXC"
PIN 31: "G2_RXD0"
PIN 32: "G2_RXD1"
PIN 33: "G2_RXD2"
PIN 34: "G2_RXD3"
PIN 35: "G2_RXDV"
PIN 36: "G2_RXC"
PIN 37: "NCEB"
PIN 38: "NWEB"
PIN 39: "NREB"
PIN 40: "NDL4"
PIN 41: "NDL5"
PIN 42: "NDL6"
PIN 43: "NDL7"
PIN 44: "NRB"
PIN 45: "NCLE"
PIN 46: "NALE"
PIN 47: "NDL0"
PIN 48: "NDL1"
PIN 49: "NDL2"
PIN 50: "NDL3"
PIN 51: "MDI_TP_P0"
PIN 52: "MDI_TN_P0"
PIN 53: "MDI_RP_P0"
PIN 54: "MDI_RN_P0"
PIN 55: "MDI_TP_P1"
PIN 56: "MDI_TN_P1"
PIN 57: "MDI_RP_P1"
PIN 58: "MDI_RN_P1"
PIN 59: "MDI_RP_P2"
PIN 60: "MDI_RN_P2"
PIN 61: "MDI_TP_P2"
PIN 62: "MDI_TN_P2"
PIN 63: "MDI_TP_P3"
PIN 64: "MDI_TN_P3"
PIN 65: "MDI_RP_P3"
PIN 66: "MDI_RN_P3"
PIN 67: "MDI_RP_P4"
PIN 68: "MDI_RN_P4"
PIN 69: "MDI_TP_P4"
PIN 70: "MDI_TN_P4"
PIN 71: "PMIC_SCL"
PIN 72: "PMIC_SDA"
PIN 73: "SPIC1_CLK"
PIN 74: "SPIC1_MOSI"
PIN 75: "SPIC1_MISO"
PIN 76: "SPIC1_CS"
PIN 77: "GPIO_D"
PIN 78: "WATCHDOG"
PIN 79: "RTS3_N"
PIN 80: "CTS3_N"
PIN 81: "TXD3"
PIN 82: "RXD3"
PIN 83: "PERST0_N"
PIN 84: "PERST1_N"
PIN 85: "WLED_N"
PIN 86: "EPHY_LED0_N"
PIN 87: "AUXIN0"
PIN 88: "AUXIN1"
PIN 89: "AUXIN2"
PIN 90: "AUXIN3"
PIN 91: "TXD4"
PIN 92: "RXD4"
PIN 93: "RTS4_N"
PIN 94: "CST4_N"
PIN 95: "PWM1"
PIN 96: "PWM2"
PIN 97: "PWM3"
PIN 98: "PWM4"
PIN 99: "PWM5"
PIN 100: "PWM6"
PIN 101: "PWM7"
PIN 102: "GPIO_E"
Valid values for function are:
"emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
"pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
Valid values for groups are:
additional data is put followingly with valid value allowing us to know which
applicable function and which relevant pins (in pin#) are able applied for that
group.
Valid value function pins (in pin#)
-------------------------------------------------------------------------
"emmc" "emmc" 40, 41, 42, 43, 44, 45,
47, 48, 49, 50
"emmc_rst" "emmc" 37
"esw" "eth" 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 67, 68,
69, 70
"esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56,
57, 58
"esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70
"rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70
"rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70
"rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30,
31, 32, 33, 34, 35, 36
"mdc_mdio" "eth" 23, 24
"i2c0" "i2c" 14, 15
"i2c1_0" "i2c" 55, 56
"i2c1_1" "i2c" 73, 74
"i2c1_2" "i2c" 87, 88
"i2c2_0" "i2c" 57, 58
"i2c2_1" "i2c" 75, 76
"i2c2_2" "i2c" 89, 90
"i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5
"i2s1_in_data" "i2s" 1
"i2s2_in_data" "i2s" 16
"i2s3_in_data" "i2s" 17
"i2s4_in_data" "i2s" 18
"i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5
"i2s1_out_data" "i2s" 2
"i2s2_out_data" "i2s" 19
"i2s3_out_data" "i2s" 20
"i2s4_out_data" "i2s" 21
"ir_0_tx" "ir" 16
"ir_1_tx" "ir" 59
"ir_2_tx" "ir" 99
"ir_0_rx" "ir" 17
"ir_1_rx" "ir" 60
"ir_2_rx" "ir" 100
"ephy_leds" "led" 86, 91, 92, 93, 94
"ephy0_led" "led" 86
"ephy1_led" "led" 91
"ephy2_led" "led" 92
"ephy3_led" "led" 93
"ephy4_led" "led" 94
"wled" "led" 85
"par_nand" "flash" 37, 38, 39, 40, 41, 42,
43, 44, 45, 46, 47, 48,
49, 50
"snfi" "flash" 8, 9, 10, 11, 12, 13
"spi_nor" "flash" 8, 9, 10, 11, 12, 13
"pcie0_0_waken" "pcie" 14
"pcie0_1_waken" "pcie" 79
"pcie1_0_waken" "pcie" 14
"pcie0_0_clkreq" "pcie" 15
"pcie0_1_clkreq" "pcie" 80
"pcie1_0_clkreq" "pcie" 15
"pcie0_pad_perst" "pcie" 83
"pcie1_pad_perst" "pcie" 84
"pmic_bus" "pmic" 71, 72
"pwm_ch1_0" "pwm" 51
"pwm_ch1_1" "pwm" 73
"pwm_ch1_2" "pwm" 95
"pwm_ch2_0" "pwm" 52
"pwm_ch2_1" "pwm" 74
"pwm_ch2_2" "pwm" 96
"pwm_ch3_0" "pwm" 53
"pwm_ch3_1" "pwm" 75
"pwm_ch3_2" "pwm" 97
"pwm_ch4_0" "pwm" 54
"pwm_ch4_1" "pwm" 67
"pwm_ch4_2" "pwm" 76
"pwm_ch4_3" "pwm" 98
"pwm_ch5_0" "pwm" 68
"pwm_ch5_1" "pwm" 77
"pwm_ch5_2" "pwm" 99
"pwm_ch6_0" "pwm" 69
"pwm_ch6_1" "pwm" 78
"pwm_ch6_2" "pwm" 81
"pwm_ch6_3" "pwm" 100
"pwm_ch7_0" "pwm" 70
"pwm_ch7_1" "pwm" 82
"pwm_ch7_2" "pwm" 101
"sd_0" "sd" 16, 17, 18, 19, 20, 21
"sd_1" "sd" 25, 26, 27, 28, 29, 30
"spic0_0" "spi" 63, 64, 65, 66
"spic0_1" "spi" 79, 80, 81, 82
"spic1_0" "spi" 67, 68, 69, 70
"spic1_1" "spi" 73, 74, 75, 76
"spic2_0_wp_hold" "spi" 8, 9
"spic2_0" "spi" 10, 11, 12, 13
"tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10
"tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13
"tdm_0_out_data" "tdm" 20
"tdm_0_in_data" "tdm" 21
"tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59
"tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62
"tdm_1_out_data" "tdm" 55
"tdm_1_in_data" "tdm" 56
"uart0_0_tx_rx" "uart" 6, 7
"uart1_0_tx_rx" "uart" 55, 56
"uart1_0_rts_cts" "uart" 57, 58
"uart1_1_tx_rx" "uart" 73, 74
"uart1_1_rts_cts" "uart" 75, 76
"uart2_0_tx_rx" "uart" 3, 4
"uart2_0_rts_cts" "uart" 1, 2
"uart2_1_tx_rx" "uart" 51, 52
"uart2_1_rts_cts" "uart" 53, 54
"uart2_2_tx_rx" "uart" 59, 60
"uart2_2_rts_cts" "uart" 61, 62
"uart2_3_tx_rx" "uart" 95, 96
"uart3_0_tx_rx" "uart" 57, 58
"uart3_1_tx_rx" "uart" 81, 82
"uart3_1_rts_cts" "uart" 79, 80
"uart4_0_tx_rx" "uart" 61, 62
"uart4_1_tx_rx" "uart" 91, 92
"uart4_1_rts_cts" "uart" 93, 94
"uart4_2_tx_rx" "uart" 97, 98
"uart4_2_rts_cts" "uart" 95, 96
"watchdog" "watchdog" 78
== Valid values for pins, function and groups on MT7629 ==
Pin #: Valid values for pins
-----------------------------
PIN 0: "TOP_5G_CLK"
PIN 1: "TOP_5G_DATA"
PIN 2: "WF0_5G_HB0"
PIN 3: "WF0_5G_HB1"
PIN 4: "WF0_5G_HB2"
PIN 5: "WF0_5G_HB3"
PIN 6: "WF0_5G_HB4"
PIN 7: "WF0_5G_HB5"
PIN 8: "WF0_5G_HB6"
PIN 9: "XO_REQ"
PIN 10: "TOP_RST_N"
PIN 11: "SYS_WATCHDOG"
PIN 12: "EPHY_LED0_N_JTDO"
PIN 13: "EPHY_LED1_N_JTDI"
PIN 14: "EPHY_LED2_N_JTMS"
PIN 15: "EPHY_LED3_N_JTCLK"
PIN 16: "EPHY_LED4_N_JTRST_N"
PIN 17: "WF2G_LED_N"
PIN 18: "WF5G_LED_N"
PIN 19: "I2C_SDA"
PIN 20: "I2C_SCL"
PIN 21: "GPIO_9"
PIN 22: "GPIO_10"
PIN 23: "GPIO_11"
PIN 24: "GPIO_12"
PIN 25: "UART1_TXD"
PIN 26: "UART1_RXD"
PIN 27: "UART1_CTS"
PIN 28: "UART1_RTS"
PIN 29: "UART2_TXD"
PIN 30: "UART2_RXD"
PIN 31: "UART2_CTS"
PIN 32: "UART2_RTS"
PIN 33: "MDI_TP_P1"
PIN 34: "MDI_TN_P1"
PIN 35: "MDI_RP_P1"
PIN 36: "MDI_RN_P1"
PIN 37: "MDI_RP_P2"
PIN 38: "MDI_RN_P2"
PIN 39: "MDI_TP_P2"
PIN 40: "MDI_TN_P2"
PIN 41: "MDI_TP_P3"
PIN 42: "MDI_TN_P3"
PIN 43: "MDI_RP_P3"
PIN 44: "MDI_RN_P3"
PIN 45: "MDI_RP_P4"
PIN 46: "MDI_RN_P4"
PIN 47: "MDI_TP_P4"
PIN 48: "MDI_TN_P4"
PIN 49: "SMI_MDC"
PIN 50: "SMI_MDIO"
PIN 51: "PCIE_PERESET_N"
PIN 52: "PWM_0"
PIN 53: "GPIO_0"
PIN 54: "GPIO_1"
PIN 55: "GPIO_2"
PIN 56: "GPIO_3"
PIN 57: "GPIO_4"
PIN 58: "GPIO_5"
PIN 59: "GPIO_6"
PIN 60: "GPIO_7"
PIN 61: "GPIO_8"
PIN 62: "SPI_CLK"
PIN 63: "SPI_CS"
PIN 64: "SPI_MOSI"
PIN 65: "SPI_MISO"
PIN 66: "SPI_WP"
PIN 67: "SPI_HOLD"
PIN 68: "UART0_TXD"
PIN 69: "UART0_RXD"
PIN 70: "TOP_2G_CLK"
PIN 71: "TOP_2G_DATA"
PIN 72: "WF0_2G_HB0"
PIN 73: "WF0_2G_HB1"
PIN 74: "WF0_2G_HB2"
PIN 75: "WF0_2G_HB3"
PIN 76: "WF0_2G_HB4"
PIN 77: "WF0_2G_HB5"
PIN 78: "WF0_2G_HB6"
Valid values for function are:
"eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart",
"watchdog", "wifi"
Valid values for groups are:
Valid value function pins (in pin#)
----------------------------------------------------------------
"mdc_mdio" "eth" 23, 24
"i2c_0" "i2c" 19, 20
"i2c_1" "i2c" 53, 54
"ephy_leds" "led" 12, 13, 14, 15, 16,
17, 18
"ephy0_led" "led" 12
"ephy1_led" "led" 13
"ephy2_led" "led" 14
"ephy3_led" "led" 15
"ephy4_led" "led" 16
"wf2g_led" "led" 17
"wf5g_led" "led" 18
"snfi" "flash" 62, 63, 64, 65, 66, 67
"spi_nor" "flash" 62, 63, 64, 65, 66, 67
"pcie_pereset" "pcie" 51
"pcie_wake" "pcie" 55
"pcie_clkreq" "pcie" 56
"pwm_0" "pwm" 52
"pwm_1" "pwm" 61
"spi_0" "spi" 21, 22, 23, 24
"spi_1" "spi" 62, 63, 64, 65
"spi_wp" "spi" 66
"spi_hold" "spi" 67
"uart0_txd_rxd" "uart" 68, 69
"uart1_0_txd_rxd" "uart" 25, 26
"uart1_0_cts_rts" "uart" 27, 28
"uart1_1_txd_rxd" "uart" 53, 54
"uart1_1_cts_rts" "uart" 55, 56
"uart2_0_txd_rxd" "uart" 29, 30
"uart2_0_cts_rts" "uart" 31, 32
"uart2_1_txd_rxd" "uart" 57, 58
"uart2_1_cts_rts" "uart" 59, 60
"watchdog" "watchdog" 11
"wf0_2g" "wifi" 70, 71, 72, 73, 74,
75, 76, 77, 78
"wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, 10
Example:
pio: pinctrl@10211000 {
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
pinctrl_eth_default: eth-default {
mux-mdio {
groups = "mdc_mdio";
function = "eth";
drive-strength = <12>;
};
mux-gmac2 {
groups = "gmac2";
function = "eth";
drive-strength = <12>;
};
mux-esw {
groups = "esw";
function = "eth";
drive-strength = <8>;
};
conf-mdio {
pins = "MDC";
bias-pull-up;
};
};
};

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* Mediatek MT8183 Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
- gpio-ranges : gpio valid number range.
- reg: physical address base for gpio base registers. There are 10 GPIO
physical address base in mt8183.
Optional properties:
- reg-names: gpio base register names. There are 10 gpio base register
names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
"iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint".
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs to sysirq.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
output-high, input-schmitt-enable, input-schmitt-disable
and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01,
10 or 11. So It needs config "mediatek,pull-up-adv" or
"mediatek,pull-down-adv" to support arguments for those special pins.
Valid arguments are from 0 to 3.
mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
It can only support 2/4/6/8/10/12/14/16mA in mt8183.
For I2C pins, there are existing generic driving setup and the specific
driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
adjustment in generic driving setup. But in specific driving setup,
they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup for I2C pins, the existing generic driving setup will be
disabled. For some special features, we need the I2C pins specific
driving setup. The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of
the generic driving property.
We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
It is used to enable or disable the specific driving setup.
E1E0 is used to describe the detail strength specification of the I2C pin.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
Examples:
#include "mt8183-pinfunc.h"
...
{
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
...
};
};

5
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@ -80,10 +80,7 @@ patternProperties:
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments which is from 0 to 7. It can only support
2/4/6/8/10/12/14/16mA in mt8195.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MDM9607 TLMM block
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
MDM9607 platform.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,mdm9607-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-mdm9607-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-mdm9607-tlmm-state"
'$defs':
qcom-mdm9607-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3 ]
minItems: 1
maxItems: 16
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3,
atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,mdm9607-tlmm";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 80>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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@ -1,288 +0,0 @@
Qualcomm PMIC GPIO block
This binding describes the GPIO block(s) found in the 8xxx series of
PMIC's from Qualcomm.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,pm8005-gpio"
"qcom,pm8018-gpio"
"qcom,pm8038-gpio"
"qcom,pm8058-gpio"
"qcom,pm8916-gpio"
"qcom,pm8917-gpio"
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8950-gpio"
"qcom,pm8994-gpio"
"qcom,pm8998-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8950-gpio"
"qcom,pmi8994-gpio"
"qcom,pmi8998-gpio"
"qcom,pms405-gpio"
"qcom,pm660-gpio"
"qcom,pm660l-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm8350-gpio"
"qcom,pm8350b-gpio"
"qcom,pm8350c-gpio"
"qcom,pmk8350-gpio"
"qcom,pm7325-gpio"
"qcom,pmr735a-gpio"
"qcom,pmr735b-gpio"
"qcom,pm6150-gpio"
"qcom,pm6150l-gpio"
"qcom,pm8008-gpio"
"qcom,pmx55-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base of the GPIO block and length.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Must contain an array of encoded interrupt specifiers for
each available GPIO
- gpio-controller:
Usage: required
Value type: <none>
Definition: Mark the device node as a GPIO controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: Must be 2;
the first cell will be used to define gpio number and the
second denotes the flags for this gpio
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin or a list of pins. This configuration can include the
mux function to select on those pin(s), and various pin configuration
parameters, as listed below.
SUBNODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio1-gpio4 for pm8005
gpio1-gpio6 for pm8018
gpio1-gpio12 for pm8038
gpio1-gpio40 for pm8058
gpio1-gpio4 for pm8916
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio8 for pm8950 (hole on gpio3)
gpio1-gpio22 for pm8994
gpio1-gpio26 for pm8998
gpio1-gpio22 for pma8084
gpio1-gpio2 for pmi8950
gpio1-gpio10 for pmi8994
gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7
and gpio8)
gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
gpio1-gpio12 for pm8150l (hole on gpio7)
gpio1-gpio10 for pm8350
gpio1-gpio8 for pm8350b
gpio1-gpio9 for pm8350c
gpio1-gpio4 for pmk8350
gpio1-gpio10 for pm7325
gpio1-gpio4 for pmr735a
gpio1-gpio4 for pmr735b
gpio1-gpio10 for pm6150
gpio1-gpio12 for pm6150l
gpio1-gpio2 for pm8008
gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Valid values are:
"normal",
"paired",
"func1",
"func2",
"dtest1",
"dtest2",
"dtest3",
"dtest4",
And following values are supported by LV/MV GPIO subtypes:
"func3",
"func4"
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <empty>
Definition: The specified pins should be configured as pull up.
- qcom,pull-up-strength:
Usage: optional
Value type: <u32>
Definition: Specifies the strength to use for pull up, if selected.
Valid values are; as defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>:
1: 30uA (PMIC_GPIO_PULL_UP_30)
2: 1.5uA (PMIC_GPIO_PULL_UP_1P5)
3: 31.5uA (PMIC_GPIO_PULL_UP_31P5)
4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30)
If this property is omitted 30uA strength will be used if
pull up is selected
- bias-high-impedance:
Usage: optional
Value type: <none>
Definition: The specified pins will put in high-Z mode and disabled.
- input-enable:
Usage: optional
Value type: <none>
Definition: The specified pins are put in input mode.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
- power-source:
Usage: optional
Value type: <u32>
Definition: Selects the power source for the specified pins. Valid
power sources are defined per chip in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
- qcom,drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins. Value
drive strengths are:
0: no (PMIC_GPIO_STRENGTH_NO)
1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V
2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V
3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V
as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h>
- drive-push-pull:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in push-pull mode.
- drive-open-drain:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in open-drain mode.
- drive-open-source:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in open-source mode.
- qcom,analog-pass:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in analog-pass-through mode.
- qcom,atest:
Usage: optional
Value type: <u32>
Definition: Selects ATEST rail to route to GPIO when it's configured
in analog-pass-through mode.
Valid values are 1-4 corresponding to ATEST1 to ATEST4.
- qcom,dtest-buffer:
Usage: optional
Value type: <u32>
Definition: Selects DTEST rail to route to GPIO when it's configured
as digital input.
Valid values are 1-4 corresponding to DTEST1 to DTEST4.
Example:
pm8921_gpio: gpio@150 {
compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio";
reg = <0x150 0x160>;
interrupts = <192 1>, <193 1>, <194 1>,
<195 1>, <196 1>, <197 1>,
<198 1>, <199 1>, <200 1>,
<201 1>, <202 1>, <203 1>,
<204 1>, <205 1>, <206 1>,
<207 1>, <208 1>, <209 1>,
<210 1>, <211 1>, <212 1>,
<213 1>, <214 1>, <215 1>,
<216 1>, <217 1>, <218 1>,
<219 1>, <220 1>, <221 1>,
<222 1>, <223 1>, <224 1>,
<225 1>, <226 1>, <227 1>,
<228 1>, <229 1>, <230 1>,
<231 1>, <232 1>, <233 1>,
<234 1>, <235 1>;
gpio-controller;
#gpio-cells = <2>;
pm8921_gpio_keys: gpio-keys {
volume-keys {
pins = "gpio20", "gpio21";
function = "normal";
input-enable;
bias-pull-up;
drive-push-pull;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8921_GPIO_S4>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PMIC GPIO block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
This binding describes the GPIO block(s) found in the 8xxx series of
PMIC's from Qualcomm.
properties:
compatible:
items:
- enum:
- qcom,pm660-gpio
- qcom,pm660l-gpio
- qcom,pm6150-gpio
- qcom,pm6150l-gpio
- qcom,pm7325-gpio
- qcom,pm8005-gpio
- qcom,pm8008-gpio
- qcom,pm8018-gpio
- qcom,pm8038-gpio
- qcom,pm8058-gpio
- qcom,pm8150-gpio
- qcom,pm8150b-gpio
- qcom,pm8350-gpio
- qcom,pm8350b-gpio
- qcom,pm8350c-gpio
- qcom,pm8916-gpio
- qcom,pm8917-gpio
- qcom,pm8921-gpio
- qcom,pm8941-gpio
- qcom,pm8950-gpio
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
- qcom,pmi8950-gpio
- qcom,pmi8994-gpio
- qcom,pmi8998-gpio
- qcom,pmk8350-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
- qcom,pms405-gpio
- qcom,pmx55-gpio
- enum:
- qcom,spmi-gpio
- qcom,ssbi-gpio
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
gpio-ranges:
maxItems: 1
'#gpio-cells':
const: 2
description:
The first cell will be used to define gpio number and the
second denotes the flags for this gpio
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- interrupt-controller
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-pmic-gpio-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-pmic-gpio-state"
$defs:
qcom-pmic-gpio-state:
type: object
allOf:
- $ref: "pinmux-node.yaml"
- $ref: "pincfg-node.yaml"
properties:
pins:
description:
List of gpio pins affected by the properties specified in
this subnode. Valid pins are
- gpio1-gpio10 for pm6150
- gpio1-gpio12 for pm6150l
- gpio1-gpio10 for pm7325
- gpio1-gpio4 for pm8005
- gpio1-gpio2 for pm8008
- gpio1-gpio6 for pm8018
- gpio1-gpio12 for pm8038
- gpio1-gpio40 for pm8058
- gpio1-gpio10 for pm8150 (holes on gpio2, gpio5,
gpio7 and gpio8)
- gpio1-gpio12 for pm8150b (holes on gpio3, gpio4
and gpio7)
- gpio1-gpio12 for pm8150l (hole on gpio7)
- gpio1-gpio4 for pm8916
- gpio1-gpio10 for pm8350
- gpio1-gpio8 for pm8350b
- gpio1-gpio9 for pm8350c
- gpio1-gpio38 for pm8917
- gpio1-gpio44 for pm8921
- gpio1-gpio36 for pm8941
- gpio1-gpio8 for pm8950 (hole on gpio3)
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio2 for pmi8950
- gpio1-gpio10 for pmi8994
- gpio1-gpio4 for pmk8350
- gpio1-gpio4 for pmr735a
- gpio1-gpio4 for pmr735b
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9
and gpio10)
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
items:
pattern: "^gpio([0-9]+)$"
function:
items:
- enum:
- normal
- paired
- func1
- func2
- dtest1
- dtest2
- dtest3
- dtest4
- func3 # supported by LV/MV GPIO subtypes
- func4 # supported by LV/MV GPIO subtypes
bias-disable: true
bias-pull-down: true
bias-pull-up: true
qcom,pull-up-strength:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies the strength to use for pull up, if selected.
Valid values are defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
If this property is omitted 30uA strength will be used
if pull up is selected
enum: [0, 1, 2, 3]
bias-high-impedance: true
input-enable: true
output-high: true
output-low: true
power-source: true
qcom,drive-strength:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects the drive strength for the specified pins
Valid drive strength values are defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
enum: [0, 1, 2, 3]
drive-push-pull: true
drive-open-drain: true
drive-open-source: true
qcom,analog-pass:
$ref: /schemas/types.yaml#/definitions/flag
description:
The specified pins are configured in
analog-pass-through mode.
qcom,atest:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects ATEST rail to route to GPIO when it's
configured in analog-pass-through mode.
enum: [1, 2, 3, 4]
qcom,dtest-buffer:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects DTEST rail to route to GPIO when it's
configured as digital input.
enum: [1, 2, 3, 4]
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
pm8921_gpio: gpio@150 {
compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio";
reg = <0x150 0x160>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
gpio-ranges = <&pm8921_gpio 0 0 44>;
#gpio-cells = <2>;
pm8921_gpio_keys: gpio-keys-state {
volume-keys {
pins = "gpio20", "gpio21";
function = "normal";
input-enable;
bias-pull-up;
drive-push-pull;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8921_GPIO_S4>;
};
};
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
maintainers:
- Iskren Chernev <iskren.chernev@gmail.com>
description:
This binding describes the Top Level Mode Multiplexer block found in the
SM4250/6115 platforms.
properties:
compatible:
const: qcom,sm6115-tlmm
reg:
minItems: 3
maxItems: 3
reg-names:
items:
- const: west
- const: south
- const: east
interrupts:
description: Specifies the TLMM summary IRQ
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
description:
Specifies the PIN numbers and Flags, as defined in defined in
include/dt-bindings/interrupt-controller/irq.h
const: 2
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
wakeup-parent:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-sm6115-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-sm6115-tlmm-state"
'$defs':
qcom-sm6115-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
wlan1_adc0, elan1_adc1 ]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x500000 0x400000>,
<0x900000 0x400000>,
<0xd00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 114>;
sdc2_on_state: sdc2-on-state {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio88";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L combined Pin and GPIO controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
enum:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
E.g. "RZG2L_GPIO(39, 1)" for P39_1.
gpio-ranges:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
items:
- description: GPIO_RSTN signal
- description: GPIO_PORT_RESETN signal
- description: GPIO_SPARE_RESETN signal
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZG2L_PORT_PINMUX()
helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
pins: true
drive-strength:
enum: [ 2, 4, 8, 12 ]
power-source:
enum: [ 1800, 2500, 3300 ]
slew-rate: true
gpio-hog: true
gpios: true
input-enable: true
output-high: true
output-low: true
line-name: true
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- clocks
- power-domains
- resets
examples:
- |
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a07g044-pinctrl";
reg = <0x11030000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
resets = <&cpg R9A07G044_GPIO_RSTN>,
<&cpg R9A07G044_GPIO_PORT_RESETN>,
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
power-domains = <&cpg>;
scif0_pins: serial0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) 0>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
<RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
power-source = <3300>;
};
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
};
};

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@ -22,6 +22,7 @@ Required Properties:
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.

1
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@ -24,6 +24,7 @@ properties:
- st,stm32f746-pinctrl
- st,stm32f769-pinctrl
- st,stm32h743-pinctrl
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl

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@ -1,105 +0,0 @@
Binding for Xilinx Zynq Pinctrl
Required properties:
- compatible: "xlnx,zynq-pinctrl"
- syscon: phandle to SLCR
- reg: Offset and length of pinctrl space in SLCR
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Zynq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Required properties for pinmux nodes are:
- groups: A list of pinmux groups.
- function: The name of a pinmux function to activate for the specified set
of groups.
Required properties for configuration nodes:
One of:
- pins: a list of pin names
- groups: A list of pinmux groups.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
groups, function
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
low-power-disable, low-power-enable
Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
respectively.
Valid values for groups are:
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp,
ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
Valid values for pins are:
MIO0 - MIO53
Valid values for function are:
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
The following driver-specific properties as defined here are valid to specify in
a pin configuration subnode:
- io-standard: Configure the pin to use the selected IO standard according to
this mapping:
1: LVCMOS18
2: LVCMOS25
3: LVCMOS33
4: HSTL
Example:
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Zynq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
properties:
compatible:
const: xlnx,zynq-pinctrl
reg:
description: Specifies the base address and size of the SLCR space.
maxItems: 1
syscon:
description:
phandle to the SLCR.
patternProperties:
'^(.*-)?(default|gpio)$':
type: object
patternProperties:
'^mux':
type: object
description:
Pinctrl node's client devices use subnodes for pin muxes,
which in turn use below standard properties.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of groups to select (either this or "pins" must be
specified), available groups for this subnode.
items:
enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp,
can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp,
can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp,
can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp,
can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp,
can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp,
can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp,
uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp,
uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp,
uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp,
uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp,
uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp,
i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp,
i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp,
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp,
i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp,
i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp,
ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp,
swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp,
swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp,
gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp,
gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp,
gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp,
gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp,
gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp,
gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp,
gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp,
gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp,
gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp,
usb1_0_grp]
maxItems: 54
function:
description:
Specify the alternative function to be configured for the
given pin groups.
enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk,
qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc,
sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0,
can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
usb0, usb1]
required:
- groups
- function
additionalProperties: false
'^conf':
type: object
description:
Pinctrl node's client devices use subnodes for pin configurations,
which in turn use the standard properties below.
$ref: pincfg-node.yaml#
properties:
groups:
description:
List of pin groups as mentioned above.
pins:
description:
List of pin names to select in this subnode.
items:
pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
maxItems: 54
bias-pull-up: true
bias-pull-down: true
bias-disable: true
bias-high-impedance: true
low-power-enable: true
low-power-disable: true
slew-rate:
enum: [0, 1]
power-source:
enum: [1, 2, 3, 4]
oneOf:
- required: [ groups ]
- required: [ pins ]
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-zynq.h>
pinctrl0: pinctrl@700 {
compatible = "xlnx,zynq-pinctrl";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};
uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
...

17
MAINTAINERS
View File

@ -14727,6 +14727,12 @@ F: Documentation/driver-api/pin-control.rst
F: drivers/pinctrl/
F: include/linux/pinctrl/
PIN CONTROLLER - AMD
M: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
S: Maintained
F: drivers/pinctrl/pinctrl-amd.c
PIN CONTROLLER - FREESCALE
M: Dong Aisheng <aisheng.dong@nxp.com>
M: Fabio Estevam <festevam@gmail.com>
@ -14745,12 +14751,19 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
F: drivers/pinctrl/intel/
PIN CONTROLLER - KEEMBAY
M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
S: Supported
F: drivers/pinctrl/pinctrl-keembay*
PIN CONTROLLER - MEDIATEK
M: Sean Wang <sean.wang@kernel.org>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
F: drivers/pinctrl/mediatek/
PIN CONTROLLER - MICROCHIP AT91

2
arch/arm/boot/dts/mt8135.dtsi
View File

@ -9,7 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt8135-resets.h>
#include "mt8135-pinfunc.h"
#include <dt-bindings/pinctrl/mt8135-pinfunc.h>
/ {
#address-cells = <2>;

2
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -14,7 +14,7 @@
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h>
#include "mt8183-pinfunc.h"
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
/ {
compatible = "mediatek,mt8183";

24
drivers/pinctrl/Kconfig
View File

@ -248,12 +248,15 @@ config PINCTRL_SX150X
- 16 bits: sx1509q, sx1506q
config PINCTRL_PISTACHIO
def_bool y if MACH_PISTACHIO
bool "IMG Pistachio SoC pinctrl driver"
depends on OF && (MIPS || COMPILE_TEST)
depends on GPIOLIB
select PINMUX
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
select OF_GPIO
help
This support pinctrl and gpio driver for IMG Pistachio SoC.
config PINCTRL_ST
bool
@ -404,6 +407,25 @@ config PINCTRL_K210
Add support for the Canaan Kendryte K210 RISC-V SOC Field
Programmable IO Array (FPIOA) controller.
config PINCTRL_KEEMBAY
tristate "Pinctrl driver for Intel Keem Bay SoC"
depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
depends on HAS_IOMEM
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select GPIOLIB_IRQCHIP
select GPIO_GENERIC
help
This selects pin control driver for the Intel Keembay SoC.
It provides pin config functions such as pullup, pulldown,
interrupt, drive strength, sec lock, schmitt trigger, slew
rate control and direction control. This module will be
called as pinctrl-keembay.
source "drivers/pinctrl/actions/Kconfig"
source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"

1
drivers/pinctrl/Makefile
View File

@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o
obj-y += actions/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/

4
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View File

@ -133,8 +133,8 @@ static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
}
/**
* Search for the signal expression needed to enable the pin's signal for the
* requested function.
* aspeed_find_expr_by_name - Search for the signal expression needed to
* enable the pin's signal for the requested function.
*
* @exprs: List of signal expressions (haystack)
* @name: The name of the requested function (needle)

3
drivers/pinctrl/aspeed/pinmux-aspeed.c
View File

@ -59,7 +59,8 @@ int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
}
/**
* Query the enabled or disabled state for a mux function's signal on a pin
* aspeed_sig_expr_eval - Query the enabled or disabled state for a
* mux function's signal on a pin
*
* @ctx: The driver context for the pinctrl IP
* @expr: An expression controlling the signal for a mux function on a pin

3
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -416,8 +416,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
}
}
/* This should not happen, every IRQ has a bank */
if (i == BCM2835_NUM_IRQS)
BUG();
BUG_ON(i == BCM2835_NUM_IRQS);
chained_irq_enter(host_chip, desc);

7
drivers/pinctrl/freescale/Kconfig
View File

@ -166,6 +166,13 @@ config PINCTRL_IMX8DXL
help
Say Y here to enable the imx8dxl pinctrl driver
config PINCTRL_IMX8ULP
tristate "IMX8ULP pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx8ulp pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610

1
drivers/pinctrl/freescale/Makefile
View File

@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o

2
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
View File

@ -155,7 +155,7 @@ static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = {
};
static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
static const struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
.pins = imx8dxl_pinctrl_pads,
.npins = ARRAY_SIZE(imx8dxl_pinctrl_pads),
.flags = IMX_USE_SCU,

2
drivers/pinctrl/freescale/pinctrl-imx8mn.c
View File

@ -317,7 +317,7 @@ static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD),
};
static struct imx_pinctrl_soc_info imx8mn_pinctrl_info = {
static const struct imx_pinctrl_soc_info imx8mn_pinctrl_info = {
.pins = imx8mn_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mn_pinctrl_pads),
.gpr_compatible = "fsl,imx8mn-iomuxc-gpr",

2
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
View File

@ -194,7 +194,7 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
};
static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
static const struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU,

278
drivers/pinctrl/freescale/pinctrl-imx8ulp.c Normal file
View File

@ -0,0 +1,278 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx8ulp_pads {
IMX8ULP_PAD_PTD0 = 0,
IMX8ULP_PAD_PTD1,
IMX8ULP_PAD_PTD2,
IMX8ULP_PAD_PTD3,
IMX8ULP_PAD_PTD4,
IMX8ULP_PAD_PTD5,
IMX8ULP_PAD_PTD6,
IMX8ULP_PAD_PTD7,
IMX8ULP_PAD_PTD8,
IMX8ULP_PAD_PTD9,
IMX8ULP_PAD_PTD10,
IMX8ULP_PAD_PTD11,
IMX8ULP_PAD_PTD12,
IMX8ULP_PAD_PTD13,
IMX8ULP_PAD_PTD14,
IMX8ULP_PAD_PTD15,
IMX8ULP_PAD_PTD16,
IMX8ULP_PAD_PTD17,
IMX8ULP_PAD_PTD18,
IMX8ULP_PAD_PTD19,
IMX8ULP_PAD_PTD20,
IMX8ULP_PAD_PTD21,
IMX8ULP_PAD_PTD22,
IMX8ULP_PAD_PTD23,
IMX8ULP_PAD_RESERVE0,
IMX8ULP_PAD_RESERVE1,
IMX8ULP_PAD_RESERVE2,
IMX8ULP_PAD_RESERVE3,
IMX8ULP_PAD_RESERVE4,
IMX8ULP_PAD_RESERVE5,
IMX8ULP_PAD_RESERVE6,
IMX8ULP_PAD_RESERVE7,
IMX8ULP_PAD_PTE0,
IMX8ULP_PAD_PTE1,
IMX8ULP_PAD_PTE2,
IMX8ULP_PAD_PTE3,
IMX8ULP_PAD_PTE4,
IMX8ULP_PAD_PTE5,
IMX8ULP_PAD_PTE6,
IMX8ULP_PAD_PTE7,
IMX8ULP_PAD_PTE8,
IMX8ULP_PAD_PTE9,
IMX8ULP_PAD_PTE10,
IMX8ULP_PAD_PTE11,
IMX8ULP_PAD_PTE12,
IMX8ULP_PAD_PTE13,
IMX8ULP_PAD_PTE14,
IMX8ULP_PAD_PTE15,
IMX8ULP_PAD_PTE16,
IMX8ULP_PAD_PTE17,
IMX8ULP_PAD_PTE18,
IMX8ULP_PAD_PTE19,
IMX8ULP_PAD_PTE20,
IMX8ULP_PAD_PTE21,
IMX8ULP_PAD_PTE22,
IMX8ULP_PAD_PTE23,
IMX8ULP_PAD_RESERVE8,
IMX8ULP_PAD_RESERVE9,
IMX8ULP_PAD_RESERVE10,
IMX8ULP_PAD_RESERVE11,
IMX8ULP_PAD_RESERVE12,
IMX8ULP_PAD_RESERVE13,
IMX8ULP_PAD_RESERVE14,
IMX8ULP_PAD_RESERVE15,
IMX8ULP_PAD_PTF0,
IMX8ULP_PAD_PTF1,
IMX8ULP_PAD_PTF2,
IMX8ULP_PAD_PTF3,
IMX8ULP_PAD_PTF4,
IMX8ULP_PAD_PTF5,
IMX8ULP_PAD_PTF6,
IMX8ULP_PAD_PTF7,
IMX8ULP_PAD_PTF8,
IMX8ULP_PAD_PTF9,
IMX8ULP_PAD_PTF10,
IMX8ULP_PAD_PTF11,
IMX8ULP_PAD_PTF12,
IMX8ULP_PAD_PTF13,
IMX8ULP_PAD_PTF14,
IMX8ULP_PAD_PTF15,
IMX8ULP_PAD_PTF16,
IMX8ULP_PAD_PTF17,
IMX8ULP_PAD_PTF18,
IMX8ULP_PAD_PTF19,
IMX8ULP_PAD_PTF20,
IMX8ULP_PAD_PTF21,
IMX8ULP_PAD_PTF22,
IMX8ULP_PAD_PTF23,
IMX8ULP_PAD_PTF24,
IMX8ULP_PAD_PTF25,
IMX8ULP_PAD_PTF26,
IMX8ULP_PAD_PTF27,
IMX8ULP_PAD_PTF28,
IMX8ULP_PAD_PTF29,
IMX8ULP_PAD_PTF30,
IMX8ULP_PAD_PTF31,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
};
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
else
reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
.pins = imx8ulp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
.gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
};
static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8ulp-iomuxc1", },
{ /* sentinel */ }
};
static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info);
}
static struct platform_driver imx8ulp_pinctrl_driver = {
.driver = {
.name = "imx8ulp-pinctrl",
.of_match_table = imx8ulp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8ulp_pinctrl_probe,
};
static int __init imx8ulp_pinctrl_init(void)
{
return platform_driver_register(&imx8ulp_pinctrl_driver);
}
arch_initcall(imx8ulp_pinctrl_init);
MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver");
MODULE_LICENSE("GPL v2");

1
drivers/pinctrl/mediatek/pinctrl-mt8365.c
View File

@ -485,7 +485,6 @@ static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pinctrl_probe,
.driver = {
.name = "mediatek-mt8365-pinctrl",
.owner = THIS_MODULE,
.of_match_table = mt8365_pctrl_match,
.pm = &mtk_eint_pm_ops,
},

16
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View File

@ -167,10 +167,14 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
"pwm", "led"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
@ -184,10 +188,6 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
18, 2, "gpio", "uart"),
PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
};
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {

545
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -104,6 +104,7 @@ enum jz_version {
ID_X1500,
ID_X1830,
ID_X2000,
ID_X2100,
};
struct ingenic_chip_info {
@ -589,6 +590,18 @@ static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
static int jz4755_uart2_data_pins[] = { 0x9f, };
static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
@ -630,6 +643,18 @@ static const struct group_desc jz4755_groups[] = {
INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
jz4755_mmc0_1bit_funcs),
INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
@ -661,6 +686,14 @@ static const struct group_desc jz4755_groups[] = {
static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4755_uart1_groups[] = { "uart1-data", };
static const char *jz4755_uart2_groups[] = { "uart2-data", };
static const char *jz4755_ssi_groups[] = {
"ssi-dt-b", "ssi-dt-f",
"ssi-dr-b", "ssi-dr-f",
"ssi-clk-b", "ssi-clk-f",
"ssi-gpc-b", "ssi-gpc-f",
"ssi-ce0-b", "ssi-ce0-f",
"ssi-ce1-b", "ssi-ce1-f",
};
static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *jz4755_i2c_groups[] = { "i2c-data", };
@ -683,6 +716,7 @@ static const struct function_desc jz4755_functions[] = {
{ "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
{ "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
{ "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
{ "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
{ "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
{ "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
{ "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
@ -710,7 +744,7 @@ static const struct ingenic_chip_info jz4755_chip_info = {
};
static const u32 jz4760_pull_ups[6] = {
0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
};
static const u32 jz4760_pull_downs[6] = {
@ -725,6 +759,58 @@ static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
@ -801,6 +887,58 @@ static const struct group_desc jz4760_groups[] = {
INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
jz4760_uart3_data_funcs),
INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
jz4760_mmc0_1bit_a_funcs),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
@ -854,6 +992,22 @@ static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4760_ssi0_groups[] = {
"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
};
static const char *jz4760_ssi1_groups[] = {
"ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
"ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
"ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
"ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
};
static const char *jz4760_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a",
"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
@ -898,6 +1052,8 @@ static const struct function_desc jz4760_functions[] = {
{ "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
{ "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
{ "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
{ "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
{ "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
{ "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
{ "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
{ "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
@ -936,11 +1092,11 @@ static const struct ingenic_chip_info jz4760_chip_info = {
};
static const u32 jz4770_pull_ups[6] = {
0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
};
static const u32 jz4770_pull_downs[6] = {
0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
};
static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
@ -1827,7 +1983,9 @@ static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
static int x1000_sfc_clk_pins[] = { 0x1a, };
static int x1000_sfc_ce_pins[] = { 0x1b, };
static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
static int x1000_ssi_dt_d_pins[] = { 0x62, };
@ -1871,8 +2029,8 @@ static int x1000_i2s_data_tx_pins[] = { 0x24, };
static int x1000_i2s_data_rx_pins[] = { 0x23, };
static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
static int x1000_i2s_sysclk_pins[] = { 0x20, };
static int x1000_dmic0_pins[] = { 0x35, 0x36, };
static int x1000_dmic1_pins[] = { 0x25, };
static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
static int x1000_dmic_if1_pins[] = { 0x25, };
static int x1000_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
@ -1901,7 +2059,9 @@ static const struct group_desc x1000_groups[] = {
INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
@ -1938,8 +2098,8 @@ static const struct group_desc x1000_groups[] = {
INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
INGENIC_PIN_GROUP("dmic0", x1000_dmic0, 0),
INGENIC_PIN_GROUP("dmic1", x1000_dmic1, 1),
INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
@ -1956,7 +2116,7 @@ static const char *x1000_uart1_groups[] = {
"uart1-data-a", "uart1-data-d", "uart1-hwflow",
};
static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
static const char *x1000_sfc_groups[] = { "sfc", };
static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
static const char *x1000_ssi_groups[] = {
"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
@ -1983,7 +2143,7 @@ static const char *x1000_i2c2_groups[] = { "i2c2-data", };
static const char *x1000_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *x1000_dmic_groups[] = { "dmic0", "dmic1", };
static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
static const char *x1000_cim_groups[] = { "cim-data", };
static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
static const char *x1000_pwm0_groups[] = { "pwm0", };
@ -2048,8 +2208,8 @@ static int x1500_i2s_data_tx_pins[] = { 0x24, };
static int x1500_i2s_data_rx_pins[] = { 0x23, };
static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
static int x1500_i2s_sysclk_pins[] = { 0x20, };
static int x1500_dmic0_pins[] = { 0x35, 0x36, };
static int x1500_dmic1_pins[] = { 0x25, };
static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
static int x1500_dmic_if1_pins[] = { 0x25, };
static int x1500_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
@ -2068,7 +2228,9 @@ static const struct group_desc x1500_groups[] = {
INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
@ -2079,8 +2241,8 @@ static const struct group_desc x1500_groups[] = {
INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
INGENIC_PIN_GROUP("dmic0", x1500_dmic0, 0),
INGENIC_PIN_GROUP("dmic1", x1500_dmic1, 1),
INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
@ -2101,7 +2263,7 @@ static const char *x1500_i2c2_groups[] = { "i2c2-data", };
static const char *x1500_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *x1500_dmic_groups[] = { "dmic0", "dmic1", };
static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
static const char *x1500_cim_groups[] = { "cim-data", };
static const char *x1500_pwm0_groups[] = { "pwm0", };
static const char *x1500_pwm1_groups[] = { "pwm1", };
@ -2151,7 +2313,9 @@ static const u32 x1830_pull_downs[4] = {
static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
static int x1830_sfc_clk_pins[] = { 0x1b, };
static int x1830_sfc_ce_pins[] = { 0x1c, };
static int x1830_ssi0_dt_pins[] = { 0x4c, };
static int x1830_ssi0_dr_pins[] = { 0x4b, };
static int x1830_ssi0_clk_pins[] = { 0x4f, };
@ -2182,8 +2346,8 @@ static int x1830_i2s_data_rx_pins[] = { 0x54, };
static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
static int x1830_i2s_sysclk_pins[] = { 0x57, };
static int x1830_dmic0_pins[] = { 0x48, 0x59, };
static int x1830_dmic1_pins[] = { 0x5a, };
static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
static int x1830_dmic_if1_pins[] = { 0x5a, };
static int x1830_lcd_tft_8bit_pins[] = {
0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x73, 0x72, 0x69,
@ -2223,7 +2387,9 @@ static const struct group_desc x1830_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
INGENIC_PIN_GROUP("sfc", x1830_sfc, 1),
INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
@ -2254,8 +2420,8 @@ static const struct group_desc x1830_groups[] = {
INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
INGENIC_PIN_GROUP("dmic0", x1830_dmic0, 2),
INGENIC_PIN_GROUP("dmic1", x1830_dmic1, 2),
INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
@ -2281,7 +2447,7 @@ static const struct group_desc x1830_groups[] = {
static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x1830_uart1_groups[] = { "uart1-data", };
static const char *x1830_sfc_groups[] = { "sfc", };
static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
static const char *x1830_ssi0_groups[] = {
"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
};
@ -2301,7 +2467,7 @@ static const char *x1830_i2c2_groups[] = { "i2c2-data", };
static const char *x1830_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
};
static const char *x1830_dmic_groups[] = { "dmic0", "dmic1", };
static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
static const char *x1830_lcd_groups[] = {
"lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
};
@ -2381,17 +2547,21 @@ static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 0x72, };
static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 0x91, };
static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
static int x2000_sfc_clk_d_pins[] = { 0x71, };
static int x2000_sfc_clk_e_pins[] = { 0x90, };
static int x2000_sfc_ce_d_pins[] = { 0x72, };
static int x2000_sfc_ce_e_pins[] = { 0x91, };
static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
static int x2000_ssi0_dt_d_pins[] = { 0x69, };
static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
static int x2000_ssi0_clk_d_pins[] = { 0x68, };
static int x2000_ssi0_ce0_b_pins[] = { 0x3c, };
static int x2000_ssi0_ce0_d_pins[] = { 0x6d, };
static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
static int x2000_ssi1_dt_d_pins[] = { 0x72, };
static int x2000_ssi1_dt_e_pins[] = { 0x91, };
@ -2401,9 +2571,9 @@ static int x2000_ssi1_dr_e_pins[] = { 0x92, };
static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
static int x2000_ssi1_clk_d_pins[] = { 0x71, };
static int x2000_ssi1_clk_e_pins[] = { 0x90, };
static int x2000_ssi1_ce0_c_pins[] = { 0x49, };
static int x2000_ssi1_ce0_d_pins[] = { 0x76, };
static int x2000_ssi1_ce0_e_pins[] = { 0x95, };
static int x2000_ssi1_ce_c_pins[] = { 0x49, };
static int x2000_ssi1_ce_d_pins[] = { 0x76, };
static int x2000_ssi1_ce_e_pins[] = { 0x95, };
static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
@ -2455,10 +2625,10 @@ static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
static int x2000_dmic0_pins[] = { 0x54, 0x55, };
static int x2000_dmic1_pins[] = { 0x56, };
static int x2000_dmic2_pins[] = { 0x57, };
static int x2000_dmic3_pins[] = { 0x58, };
static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
static int x2000_dmic_if1_pins[] = { 0x56, };
static int x2000_dmic_if2_pins[] = { 0x57, };
static int x2000_dmic_if3_pins[] = { 0x58, };
static int x2000_cim_8bit_pins[] = {
0x0e, 0x0c, 0x0d, 0x4f,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
@ -2545,17 +2715,21 @@ static const struct group_desc x2000_groups[] = {
INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
INGENIC_PIN_GROUP("sfc0-d", x2000_sfc0_d, 1),
INGENIC_PIN_GROUP("sfc0-e", x2000_sfc0_e, 0),
INGENIC_PIN_GROUP("sfc1", x2000_sfc1, 1),
INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-ce0-b", x2000_ssi0_ce0_b, 1),
INGENIC_PIN_GROUP("ssi0-ce0-d", x2000_ssi0_ce0_d, 1),
INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
@ -2565,9 +2739,9 @@ static const struct group_desc x2000_groups[] = {
INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
INGENIC_PIN_GROUP("ssi1-ce0-c", x2000_ssi1_ce0_c, 2),
INGENIC_PIN_GROUP("ssi1-ce0-d", x2000_ssi1_ce0_d, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e", x2000_ssi1_ce0_e, 1),
INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
@ -2612,10 +2786,10 @@ static const struct group_desc x2000_groups[] = {
INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
INGENIC_PIN_GROUP("dmic0", x2000_dmic0, 0),
INGENIC_PIN_GROUP("dmic1", x2000_dmic1, 0),
INGENIC_PIN_GROUP("dmic2", x2000_dmic2, 0),
INGENIC_PIN_GROUP("dmic3", x2000_dmic3, 0),
INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
x2000_cim_8bit_funcs),
INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
@ -2670,18 +2844,21 @@ static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
static const char *x2000_uart8_groups[] = { "uart8-data", };
static const char *x2000_uart9_groups[] = { "uart9-data", };
static const char *x2000_sfc_groups[] = { "sfc0-d", "sfc0-e", "sfc1", };
static const char *x2000_sfc_groups[] = {
"sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
"sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
};
static const char *x2000_ssi0_groups[] = {
"ssi0-dt-b", "ssi0-dt-d",
"ssi0-dr-b", "ssi0-dr-d",
"ssi0-clk-b", "ssi0-clk-d",
"ssi0-ce0-b", "ssi0-ce0-d",
"ssi0-ce-b", "ssi0-ce-d",
};
static const char *x2000_ssi1_groups[] = {
"ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
"ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
"ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
"ssi1-ce0-c", "ssi1-ce0-d", "ssi1-ce0-e",
"ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
};
static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
@ -2711,7 +2888,9 @@ static const char *x2000_i2s3_groups[] = {
"i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
"i2s3-clk-tx", "i2s3-sysclk-tx",
};
static const char *x2000_dmic_groups[] = { "dmic0", "dmic1", "dmic2", "dmic3", };
static const char *x2000_dmic_groups[] = {
"dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
};
static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
static const char *x2000_lcd_groups[] = {
"lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
@ -2802,6 +2981,216 @@ static const struct ingenic_chip_info x2000_chip_info = {
.pull_downs = x2000_pull_downs,
};
static const u32 x2100_pull_ups[5] = {
0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
};
static const u32 x2100_pull_downs[5] = {
0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
};
static int x2100_mac_pins[] = {
0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
};
static const struct group_desc x2100_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
x2000_cim_8bit_funcs),
INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
INGENIC_PIN_GROUP("mac", x2100_mac, 1),
};
static const char *x2100_mac_groups[] = { "mac", };
static const struct function_desc x2100_functions[] = {
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
{ "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
};
static const struct ingenic_chip_info x2100_chip_info = {
.num_chips = 5,
.reg_offset = 0x100,
.version = ID_X2100,
.groups = x2100_groups,
.num_groups = ARRAY_SIZE(x2100_groups),
.functions = x2100_functions,
.num_functions = ARRAY_SIZE(x2100_functions),
.pull_ups = x2100_pull_ups,
.pull_downs = x2100_pull_downs,
};
static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
{
unsigned int val;
@ -3441,17 +3830,17 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
{
if (jzpc->info->version >= ID_X2000) {
switch (bias) {
case PIN_CONFIG_BIAS_PULL_UP:
case GPIO_PULL_UP:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
case GPIO_PULL_DOWN:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
break;
case PIN_CONFIG_BIAS_DISABLE:
case GPIO_PULL_DIS:
default:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
@ -3654,19 +4043,20 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = {
.reg_stride = 4,
};
static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
{ .compatible = "ingenic,jz4730-gpio", },
{ .compatible = "ingenic,jz4740-gpio", },
{ .compatible = "ingenic,jz4725b-gpio", },
{ .compatible = "ingenic,jz4750-gpio", },
{ .compatible = "ingenic,jz4755-gpio", },
{ .compatible = "ingenic,jz4760-gpio", },
{ .compatible = "ingenic,jz4770-gpio", },
{ .compatible = "ingenic,jz4775-gpio", },
{ .compatible = "ingenic,jz4780-gpio", },
{ .compatible = "ingenic,x1000-gpio", },
{ .compatible = "ingenic,x1830-gpio", },
{ .compatible = "ingenic,x2000-gpio", },
static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
{ .compatible = "ingenic,jz4730-gpio" },
{ .compatible = "ingenic,jz4740-gpio" },
{ .compatible = "ingenic,jz4725b-gpio" },
{ .compatible = "ingenic,jz4750-gpio" },
{ .compatible = "ingenic,jz4755-gpio" },
{ .compatible = "ingenic,jz4760-gpio" },
{ .compatible = "ingenic,jz4770-gpio" },
{ .compatible = "ingenic,jz4775-gpio" },
{ .compatible = "ingenic,jz4780-gpio" },
{ .compatible = "ingenic,x1000-gpio" },
{ .compatible = "ingenic,x1830-gpio" },
{ .compatible = "ingenic,x2000-gpio" },
{ .compatible = "ingenic,x2100-gpio" },
{},
};
@ -3759,6 +4149,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
void __iomem *base;
const struct ingenic_chip_info *chip_info;
struct device_node *node;
struct regmap_config regmap_config;
unsigned int i;
int err;
@ -3776,8 +4167,10 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
jzpc->map = devm_regmap_init_mmio(dev, base,
&ingenic_pinctrl_regmap_config);
regmap_config = ingenic_pinctrl_regmap_config;
regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset;
jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);
if (IS_ERR(jzpc->map)) {
dev_err(dev, "Failed to create regmap\n");
return PTR_ERR(jzpc->map);
@ -3843,7 +4236,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
dev_set_drvdata(dev, jzpc->map);
for_each_child_of_node(dev->of_node, node) {
if (of_match_node(ingenic_gpio_of_match, node)) {
if (of_match_node(ingenic_gpio_of_matches, node)) {
err = ingenic_gpio_probe(jzpc, node);
if (err) {
of_node_put(node);
@ -3857,7 +4250,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
#define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr))
static const struct of_device_id ingenic_pinctrl_of_match[] = {
static const struct of_device_id ingenic_pinctrl_of_matches[] = {
{
.compatible = "ingenic,jz4730-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
@ -3922,13 +4315,17 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
.compatible = "ingenic,x2000e-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
},
{
.compatible = "ingenic,x2100-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
},
{ /* sentinel */ },
};
static struct platform_driver ingenic_pinctrl_driver = {
.driver = {
.name = "pinctrl-ingenic",
.of_match_table = ingenic_pinctrl_of_match,
.of_match_table = ingenic_pinctrl_of_matches,
},
};

1731
drivers/pinctrl/pinctrl-keembay.c Normal file
View File

File diff suppressed because it is too large Load Diff

21
drivers/pinctrl/pinctrl-single.c
View File

@ -1115,7 +1115,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
{
const char *name = "pinctrl-single,bits";
struct pcs_func_vals *vals;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
int npins_in_row;
struct pcs_function *function = NULL;
@ -1125,6 +1125,11 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
return -EINVAL;
}
if (PCS_HAS_PINCONF) {
dev_err(pcs->dev, "pinconf not supported\n");
return -ENOTSUPP;
}
npins_in_row = pcs->width / pcs->bits_per_pin;
vals = devm_kzalloc(pcs->dev,
@ -1212,29 +1217,19 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
goto free_pins;
}
gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (gsel < 0) {
res = gsel;
res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (res < 0)
goto free_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
if (PCS_HAS_PINCONF) {
dev_err(pcs->dev, "pinconf not supported\n");
goto free_pingroups;
}
*num_maps = 1;
mutex_unlock(&pcs->mutex);
return 0;
free_pingroups:
pinctrl_generic_remove_group(pcs->pctl, gsel);
*num_maps = 1;
free_function:
pinmux_generic_remove_function(pcs->pctl, fsel);
free_pins:

6
drivers/pinctrl/pinctrl-stmfx.c
View File

@ -566,7 +566,7 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
u8 pending[NR_GPIO_REGS];
u8 src[NR_GPIO_REGS] = {0, 0, 0};
unsigned long n, status;
int ret;
int i, ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
&pending, NR_GPIO_REGS);
@ -576,7 +576,9 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
src, NR_GPIO_REGS);
status = *(unsigned long *)pending;
BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
status |= (unsigned long)pending[i] << (i * 8);
for_each_set_bit(n, &status, gc->ngpio) {
handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
stmfx_pinctrl_irq_toggle_trigger(pctl, n);

2
drivers/pinctrl/pinctrl-zynq.c
View File

@ -1028,6 +1028,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
break;
}
case PIN_CONFIG_IOSTANDARD:
case PIN_CONFIG_POWER_SOURCE:
arg = zynq_pinconf_iostd_get(reg);
break;
default:
@ -1078,6 +1079,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_IOSTANDARD:
case PIN_CONFIG_POWER_SOURCE:
if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
dev_warn(pctldev->dev,
"unsupported IO standard '%u'\n",

10
drivers/pinctrl/pinctrl-zynqmp.c
View File

@ -866,15 +866,6 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev)
return ret;
}
static int zynqmp_pinctrl_remove(struct platform_device *pdev)
{
struct zynqmp_pinctrl *pctrl = platform_get_drvdata(pdev);
pinctrl_unregister(pctrl->pctrl);
return 0;
}
static const struct of_device_id zynqmp_pinctrl_of_match[] = {
{ .compatible = "xlnx,zynqmp-pinctrl" },
{ }
@ -887,7 +878,6 @@ static struct platform_driver zynqmp_pinctrl_driver = {
.of_match_table = zynqmp_pinctrl_of_match,
},
.probe = zynqmp_pinctrl_probe,
.remove = zynqmp_pinctrl_remove,
};
module_platform_driver(zynqmp_pinctrl_driver);

17
drivers/pinctrl/qcom/Kconfig
View File

@ -88,6 +88,14 @@ config PINCTRL_MSM8960
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8960 platform.
config PINCTRL_MDM9607
tristate "Qualcomm 9607 pin controller driver"
depends on GPIOLIB && OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9607 platform.
config PINCTRL_MDM9615
tristate "Qualcomm 9615 pin controller driver"
depends on OF
@ -256,6 +264,15 @@ config PINCTRL_SDX55
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX55 platform.
config PINCTRL_SM6115
tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"
depends on GPIOLIB && OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6115 and SM4250 platforms.
config PINCTRL_SM6125
tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
depends on OF

2
drivers/pinctrl/qcom/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
@ -30,6 +31,7 @@ obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o

1087
drivers/pinctrl/qcom/pinctrl-mdm9607.c Normal file
View File

File diff suppressed because it is too large Load Diff

923
drivers/pinctrl/qcom/pinctrl-sm6115.c Normal file
View File

@ -0,0 +1,923 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
static const char * const sm6115_tiles[] = {
"south",
"east",
"west"
};
enum {
SOUTH,
EAST,
WEST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9 \
}, \
.nfuncs = 10, \
.ctl_reg = 0x1000 * id, \
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = _tile, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
.oe_bit = -1, \
.in_bit = -1, \
.out_bit = -1, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = WEST, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \
.oe_bit = -1, \
.in_bit = -1, \
.out_bit = 0, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
static const struct pinctrl_pin_desc sm6115_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
PINCTRL_PIN(110, "GPIO_110"),
PINCTRL_PIN(111, "GPIO_111"),
PINCTRL_PIN(112, "GPIO_112"),
PINCTRL_PIN(113, "UFS_RESET"),
PINCTRL_PIN(114, "SDC1_RCLK"),
PINCTRL_PIN(115, "SDC1_CLK"),
PINCTRL_PIN(116, "SDC1_CMD"),
PINCTRL_PIN(117, "SDC1_DATA"),
PINCTRL_PIN(118, "SDC2_CLK"),
PINCTRL_PIN(119, "SDC2_CMD"),
PINCTRL_PIN(120, "SDC2_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
DECLARE_MSM_GPIO_PINS(54);
DECLARE_MSM_GPIO_PINS(55);
DECLARE_MSM_GPIO_PINS(56);
DECLARE_MSM_GPIO_PINS(57);
DECLARE_MSM_GPIO_PINS(58);
DECLARE_MSM_GPIO_PINS(59);
DECLARE_MSM_GPIO_PINS(60);
DECLARE_MSM_GPIO_PINS(61);
DECLARE_MSM_GPIO_PINS(62);
DECLARE_MSM_GPIO_PINS(63);
DECLARE_MSM_GPIO_PINS(64);
DECLARE_MSM_GPIO_PINS(65);
DECLARE_MSM_GPIO_PINS(66);
DECLARE_MSM_GPIO_PINS(67);
DECLARE_MSM_GPIO_PINS(68);
DECLARE_MSM_GPIO_PINS(69);
DECLARE_MSM_GPIO_PINS(70);
DECLARE_MSM_GPIO_PINS(71);
DECLARE_MSM_GPIO_PINS(72);
DECLARE_MSM_GPIO_PINS(73);
DECLARE_MSM_GPIO_PINS(74);
DECLARE_MSM_GPIO_PINS(75);
DECLARE_MSM_GPIO_PINS(76);
DECLARE_MSM_GPIO_PINS(77);
DECLARE_MSM_GPIO_PINS(78);
DECLARE_MSM_GPIO_PINS(79);
DECLARE_MSM_GPIO_PINS(80);
DECLARE_MSM_GPIO_PINS(81);
DECLARE_MSM_GPIO_PINS(82);
DECLARE_MSM_GPIO_PINS(83);
DECLARE_MSM_GPIO_PINS(84);
DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
DECLARE_MSM_GPIO_PINS(88);
DECLARE_MSM_GPIO_PINS(89);
DECLARE_MSM_GPIO_PINS(90);
DECLARE_MSM_GPIO_PINS(91);
DECLARE_MSM_GPIO_PINS(92);
DECLARE_MSM_GPIO_PINS(93);
DECLARE_MSM_GPIO_PINS(94);
DECLARE_MSM_GPIO_PINS(95);
DECLARE_MSM_GPIO_PINS(96);
DECLARE_MSM_GPIO_PINS(97);
DECLARE_MSM_GPIO_PINS(98);
DECLARE_MSM_GPIO_PINS(99);
DECLARE_MSM_GPIO_PINS(100);
DECLARE_MSM_GPIO_PINS(101);
DECLARE_MSM_GPIO_PINS(102);
DECLARE_MSM_GPIO_PINS(103);
DECLARE_MSM_GPIO_PINS(104);
DECLARE_MSM_GPIO_PINS(105);
DECLARE_MSM_GPIO_PINS(106);
DECLARE_MSM_GPIO_PINS(107);
DECLARE_MSM_GPIO_PINS(108);
DECLARE_MSM_GPIO_PINS(109);
DECLARE_MSM_GPIO_PINS(110);
DECLARE_MSM_GPIO_PINS(111);
DECLARE_MSM_GPIO_PINS(112);
static const unsigned int ufs_reset_pins[] = { 113 };
static const unsigned int sdc1_rclk_pins[] = { 114 };
static const unsigned int sdc1_clk_pins[] = { 115 };
static const unsigned int sdc1_cmd_pins[] = { 116 };
static const unsigned int sdc1_data_pins[] = { 117 };
static const unsigned int sdc2_clk_pins[] = { 118 };
static const unsigned int sdc2_cmd_pins[] = { 119 };
static const unsigned int sdc2_data_pins[] = { 120 };
enum sm6115_functions {
msm_mux_adsp_ext,
msm_mux_agera_pll,
msm_mux_atest,
msm_mux_cam_mclk,
msm_mux_cci_async,
msm_mux_cci_i2c,
msm_mux_cci_timer,
msm_mux_cri_trng,
msm_mux_dac_calib,
msm_mux_dbg_out,
msm_mux_ddr_bist,
msm_mux_ddr_pxi0,
msm_mux_ddr_pxi1,
msm_mux_ddr_pxi2,
msm_mux_ddr_pxi3,
msm_mux_gcc_gp1,
msm_mux_gcc_gp2,
msm_mux_gcc_gp3,
msm_mux_gpio,
msm_mux_gp_pdm0,
msm_mux_gp_pdm1,
msm_mux_gp_pdm2,
msm_mux_gsm0_tx,
msm_mux_gsm1_tx,
msm_mux_jitter_bist,
msm_mux_mdp_vsync,
msm_mux_mdp_vsync_out_0,
msm_mux_mdp_vsync_out_1,
msm_mux_mpm_pwr,
msm_mux_mss_lte,
msm_mux_m_voc,
msm_mux_nav_gpio,
msm_mux_pa_indicator,
msm_mux_pbs,
msm_mux_pbs_out,
msm_mux_phase_flag,
msm_mux_pll_bist,
msm_mux_pll_bypassnl,
msm_mux_pll_reset,
msm_mux_prng_rosc,
msm_mux_qdss_cti,
msm_mux_qdss_gpio,
msm_mux_qup0,
msm_mux_qup1,
msm_mux_qup2,
msm_mux_qup3,
msm_mux_qup4,
msm_mux_qup5,
msm_mux_sdc1_tb,
msm_mux_sdc2_tb,
msm_mux_sd_write,
msm_mux_ssbi_wtr1,
msm_mux_tgu,
msm_mux_tsense_pwm,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
msm_mux_uim1_reset,
msm_mux_uim2_clk,
msm_mux_uim2_data,
msm_mux_uim2_present,
msm_mux_uim2_reset,
msm_mux_usb_phy,
msm_mux_vfr_1,
msm_mux_vsense_trigger,
msm_mux_wlan1_adc0,
msm_mux_wlan1_adc1,
msm_mux__,
};
static const char * const qup0_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86",
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
"gpio111", "gpio112",
};
static const char * const ddr_bist_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
};
static const char * const phase_flag_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
"gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24",
"gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
"gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64",
"gpio102", "gpio103", "gpio104", "gpio105",
};
static const char * const qdss_gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
"gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
"gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91",
"gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107",
"gpio109", "gpio110",
};
static const char * const atest_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30",
"gpio31", "gpio32", "gpio33", "gpio86", "gpio87", "gpio88", "gpio89",
"gpio100", "gpio101",
};
static const char * const mpm_pwr_groups[] = {
"gpio1",
};
static const char * const m_voc_groups[] = {
"gpio0",
};
static const char * const dac_calib_groups[] = {
"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio14", "gpio15",
"gpio16", "gpio17", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio80", "gpio81",
"gpio82", "gpio102", "gpio103", "gpio104", "gpio105"
};
static const char * const qup1_groups[] = {
"gpio4", "gpio5", "gpio69", "gpio70",
};
static const char * const cri_trng_groups[] = {
"gpio4", "gpio5", "gpio18",
};
static const char * const qup2_groups[] = {
"gpio6", "gpio7", "gpio71", "gpio80",
};
static const char * const qup3_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11",
};
static const char * const pbs_out_groups[] = {
"gpio8", "gpio9", "gpio52",
};
static const char * const pll_bist_groups[] = {
"gpio8", "gpio9",
};
static const char * const tsense_pwm_groups[] = {
"gpio8",
};
static const char * const agera_pll_groups[] = {
"gpio10", "gpio11",
};
static const char * const pbs_groups[] = {
"gpio10", "gpio11", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
"gpio23", "gpio24", "gpio25", "gpio26", "gpio47", "gpio48", "gpio87",
"gpio90", "gpio91",
};
static const char * const qup4_groups[] = {
"gpio12", "gpio13", "gpio96", "gpio97",
};
static const char * const tgu_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15",
};
static const char * const qup5_groups[] = {
"gpio14", "gpio15", "gpio16", "gpio17",
};
static const char * const sdc2_tb_groups[] = {
"gpio18",
};
static const char * const sdc1_tb_groups[] = {
"gpio19",
};
static const char * const cam_mclk_groups[] = {
"gpio20", "gpio21", "gpio27", "gpio28",
};
static const char * const adsp_ext_groups[] = {
"gpio21",
};
static const char * const cci_i2c_groups[] = {
"gpio22", "gpio23", "gpio29", "gpio30",
};
static const char * const prng_rosc_groups[] = {
"gpio22", "gpio23",
};
static const char * const cci_timer_groups[] = {
"gpio24", "gpio25", "gpio28", "gpio32",
};
static const char * const gcc_gp1_groups[] = {
"gpio24", "gpio86",
};
static const char * const cci_async_groups[] = {
"gpio25",
};
static const char * const vsense_trigger_groups[] = {
"gpio26",
};
static const char * const qdss_cti_groups[] = {
"gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97",
};
static const char * const gp_pdm0_groups[] = {
"gpio31", "gpio95",
};
static const char * const gp_pdm1_groups[] = {
"gpio32", "gpio96",
};
static const char * const gp_pdm2_groups[] = {
"gpio33", "gpio97",
};
static const char * const nav_gpio_groups[] = {
"gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106",
"gpio107", "gpio108",
};
static const char * const vfr_1_groups[] = {
"gpio48",
};
static const char * const pa_indicator_groups[] = {
"gpio49",
};
static const char * const gsm1_tx_groups[] = {
"gpio53",
};
static const char * const ssbi_wtr1_groups[] = {
"gpio59", "gpio60",
};
static const char * const pll_bypassnl_groups[] = {
"gpio62",
};
static const char * const pll_reset_groups[] = {
"gpio63",
};
static const char * const ddr_pxi0_groups[] = {
"gpio63", "gpio64",
};
static const char * const gsm0_tx_groups[] = {
"gpio64",
};
static const char * const gcc_gp2_groups[] = {
"gpio69", "gpio107",
};
static const char * const ddr_pxi1_groups[] = {
"gpio69", "gpio70",
};
static const char * const gcc_gp3_groups[] = {
"gpio70", "gpio106",
};
static const char * const dbg_out_groups[] = {
"gpio71",
};
static const char * const uim2_data_groups[] = {
"gpio72",
};
static const char * const uim2_clk_groups[] = {
"gpio73",
};
static const char * const uim2_reset_groups[] = {
"gpio74",
};
static const char * const uim2_present_groups[] = {
"gpio75",
};
static const char * const uim1_data_groups[] = {
"gpio76",
};
static const char * const uim1_clk_groups[] = {
"gpio77",
};
static const char * const uim1_reset_groups[] = {
"gpio78",
};
static const char * const uim1_present_groups[] = {
"gpio79",
};
static const char * const mdp_vsync_groups[] = {
"gpio81", "gpio96", "gpio97",
};
static const char * const mdp_vsync_out_0_groups[] = {
"gpio81",
};
static const char * const mdp_vsync_out_1_groups[] = {
"gpio81",
};
static const char * const usb_phy_groups[] = {
"gpio89",
};
static const char * const mss_lte_groups[] = {
"gpio90", "gpio91",
};
static const char * const wlan1_adc0_groups[] = {
"gpio94",
};
static const char * const wlan1_adc1_groups[] = {
"gpio95",
};
static const char * const sd_write_groups[] = {
"gpio96",
};
static const char * const jitter_bist_groups[] = {
"gpio96", "gpio97",
};
static const char * const ddr_pxi2_groups[] = {
"gpio102", "gpio103",
};
static const char * const ddr_pxi3_groups[] = {
"gpio104", "gpio105",
};
static const struct msm_function sm6115_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer),
FUNCTION(cri_trng),
FUNCTION(dac_calib),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gsm0_tx),
FUNCTION(gsm1_tx),
FUNCTION(jitter_bist),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync_out_0),
FUNCTION(mdp_vsync_out_1),
FUNCTION(mpm_pwr),
FUNCTION(mss_lte),
FUNCTION(m_voc),
FUNCTION(nav_gpio),
FUNCTION(pa_indicator),
FUNCTION(pbs),
FUNCTION(pbs_out),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(sdc1_tb),
FUNCTION(sdc2_tb),
FUNCTION(sd_write),
FUNCTION(ssbi_wtr1),
FUNCTION(tgu),
FUNCTION(tsense_pwm),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
};
/* Every pin is maintained as a single group, and missing or non-existing pin
* would be maintained as dummy group to synchronize pin group index with
* pin descriptor registered with pinctrl core.
* Clients would not be able to request these dummy pin groups.
*/
static const struct msm_pingroup sm6115_groups[] = {
[0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
[1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
[2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
[3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
[4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _),
[5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _),
[6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _),
[7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _),
[8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _),
[9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _),
[10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _),
[11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _),
[12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _),
[13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _),
[14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
[15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
[16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
[17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
[18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _),
[19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _),
[20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _),
[21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _),
[22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
[23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
[24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
[25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
[26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _),
[27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _),
[28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _),
[29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
[30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
[31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _),
[32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _),
[33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _),
[34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _),
[35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _),
[36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _),
[37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _),
[38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _),
[39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _),
[40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _),
[41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _),
[42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _),
[43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _),
[44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _),
[45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _),
[46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _),
[47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _),
[48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _),
[49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _),
[50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _),
[51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _),
[52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _),
[53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _),
[54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _),
[55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _),
[56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _),
[57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _),
[58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _),
[59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _),
[60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _),
[61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _),
[62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _),
[63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _),
[64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _),
[65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _),
[66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _),
[67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _),
[68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _),
[69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _),
[70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _),
[71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _),
[72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _),
[73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _),
[74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _),
[75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _),
[76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _),
[77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _),
[78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _),
[79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _),
[80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _),
[81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _),
[82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _),
[83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _),
[84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _),
[85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _),
[86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _),
[87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _),
[88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _),
[89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _),
[90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _),
[91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _),
[92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _),
[93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _),
[94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _),
[95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
[96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
[97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
[98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _),
[99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _),
[100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _),
[101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _),
[102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
[103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
[104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
[105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
[106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
[107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
[108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _),
[109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),
[110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),
[111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _),
[112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _),
[113] = UFS_RESET(ufs_reset, 0x78000),
[114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),
[115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),
[116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3),
[117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0),
[118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6),
[119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3),
[120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0),
};
static const struct msm_pinctrl_soc_data sm6115_tlmm = {
.pins = sm6115_pins,
.npins = ARRAY_SIZE(sm6115_pins),
.functions = sm6115_functions,
.nfunctions = ARRAY_SIZE(sm6115_functions),
.groups = sm6115_groups,
.ngroups = ARRAY_SIZE(sm6115_groups),
.ngpios = 114,
.tiles = sm6115_tiles,
.ntiles = ARRAY_SIZE(sm6115_tiles),
};
static int sm6115_tlmm_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &sm6115_tlmm);
}
static const struct of_device_id sm6115_tlmm_of_match[] = {
{ .compatible = "qcom,sm6115-tlmm", },
{ }
};
static struct platform_driver sm6115_tlmm_driver = {
.driver = {
.name = "sm6115-tlmm",
.of_match_table = sm6115_tlmm_of_match,
},
.probe = sm6115_tlmm_probe,
.remove = msm_pinctrl_remove,
};
static int __init sm6115_tlmm_init(void)
{
return platform_driver_register(&sm6115_tlmm_driver);
}
arch_initcall(sm6115_tlmm_init);
static void __exit sm6115_tlmm_exit(void)
{
platform_driver_unregister(&sm6115_tlmm_driver);
}
module_exit(sm6115_tlmm_exit);
MODULE_DESCRIPTION("QTI sm6115 tlmm driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match);

37
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1104,39 +1104,42 @@ static int pmic_gpio_remove(struct platform_device *pdev)
}
static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
/* pm8950 has 8 GPIOs with holes on 3 */
{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
/* pm8150l has 12 GPIOs with holes on 7 */
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
/* pm8950 has 8 GPIOs with holes on 3 */
{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
{ },

11
drivers/pinctrl/renesas/Kconfig
View File

@ -37,6 +37,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_RZG2L if ARCH_R9A07G044
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@ -176,6 +177,16 @@ config PINCTRL_RZA2
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZG2L
bool "pin control support for RZ/G2L" if COMPILE_TEST
depends on OF
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
config PINCTRL_PFC_R8A77470
bool "pin control support for RZ/G1C" if COMPILE_TEST
select PINCTRL_SH_PFC

1
drivers/pinctrl/renesas/Makefile
View File

@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
ifeq ($(CONFIG_COMPILE_TEST),y)

33
drivers/pinctrl/renesas/core.c
View File

@ -571,19 +571,23 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7794_pinmux_info,
},
#endif
/* Both r8a7795 entries must be present to make sanity checks work */
#ifdef CONFIG_PINCTRL_PFC_R8A77950
{
.compatible = "renesas,pfc-r8a7795",
.data = &r8a77950_pinmux_info,
},
#endif
/*
* Both r8a7795 entries must be present to make sanity checks work, but only
* the first entry is actually used.
* R-Car H3 ES1.x is matched using soc_device_match() instead.
*/
#ifdef CONFIG_PINCTRL_PFC_R8A77951
{
.compatible = "renesas,pfc-r8a7795",
.data = &r8a77951_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77950
{
.compatible = "renesas,pfc-r8a7795",
.data = &r8a77950_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77960
{
.compatible = "renesas,pfc-r8a7796",
@ -1085,26 +1089,20 @@ static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
#ifdef CONFIG_OF
static const void *sh_pfc_quirk_match(void)
{
#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
defined(CONFIG_PINCTRL_PFC_R8A77951)
#ifdef CONFIG_PINCTRL_PFC_R8A77950
const struct soc_device_attribute *match;
static const struct soc_device_attribute quirks[] = {
{
.soc_id = "r8a7795", .revision = "ES1.*",
.data = &r8a77950_pinmux_info,
},
{
.soc_id = "r8a7795",
.data = &r8a77951_pinmux_info,
},
{ /* sentinel */ }
};
match = soc_device_match(quirks);
if (match)
return match->data ?: ERR_PTR(-ENODEV);
#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
return match->data;
#endif /* CONFIG_PINCTRL_PFC_R8A77950 */
return NULL;
}
@ -1119,9 +1117,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
#ifdef CONFIG_OF
if (pdev->dev.of_node) {
info = sh_pfc_quirk_match();
if (IS_ERR(info))
return PTR_ERR(info);
if (!info)
info = of_device_get_match_data(&pdev->dev);
} else

320
drivers/pinctrl/renesas/pfc-r8a77995.c
View File

@ -14,16 +14,27 @@
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_9(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_21(5, fn, sfx), \
PORT_GP_14(6, fn, sfx)
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
/*
* F_() : just information
@ -930,8 +941,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------- */
@ -2834,6 +2854,214 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
return bit;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
[ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */
[ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */
[ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */
[ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */
[ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */
[ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */
[ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */
[ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */
[ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
[10] = PIN_MLB_REF, /* MLB_REF */
[11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
[12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
[13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
[14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
[15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
[16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
[17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
[18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
[19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
[21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[22] = PIN_FSCLKST_N, /* FSCLKST# */
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = PIN_TDI, /* TDI */
[29] = PIN_TMS, /* TMS */
[30] = PIN_TCK, /* TCK */
[31] = PIN_TRST_N, /* TRST# */
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
[ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
[ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */
[ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */
[ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */
[ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */
[ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */
[ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */
[ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */
[ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */
[ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
[10] = RCAR_GP_PIN(1, 31), /* QPOLB */
[11] = RCAR_GP_PIN(1, 30), /* QPOLA */
[12] = RCAR_GP_PIN(1, 29), /* DU_CDE */
[13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */
[14] = RCAR_GP_PIN(1, 27), /* DU_DISP */
[15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */
[16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */
[17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */
[18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */
[19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */
[20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */
[21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */
[22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */
[23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */
[24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */
[25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */
[26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */
[27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */
[28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */
[29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */
[30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */
[31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
[ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */
[ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */
[ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */
[ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */
[ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */
[ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */
[ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */
[ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
[ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
[10] = RCAR_GP_PIN(2, 31), /* NFCE# */
[11] = RCAR_GP_PIN(2, 30), /* NFCLE */
[12] = RCAR_GP_PIN(2, 29), /* NFALE */
[13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */
[14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */
[15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */
[16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */
[17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */
[18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */
[19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */
[20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */
[21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */
[22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */
[23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */
[24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */
[25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */
[26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */
[27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */
[28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */
[29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */
[30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */
[31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
[ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */
[ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */
[ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
[ 4] = RCAR_GP_PIN(4, 27), /* TX2 */
[ 5] = RCAR_GP_PIN(4, 26), /* RX2 */
[ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */
[ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */
[ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */
[ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
[10] = RCAR_GP_PIN(4, 21), /* TX0_A */
[11] = RCAR_GP_PIN(4, 20), /* RX0_A */
[12] = RCAR_GP_PIN(4, 19), /* SCK0_A */
[13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */
[14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */
[15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */
[16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */
[17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */
[18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */
[19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */
[20] = RCAR_GP_PIN(4, 11), /* SDA1 */
[21] = RCAR_GP_PIN(4, 10), /* SCL1 */
[22] = RCAR_GP_PIN(4, 9), /* SDA0 */
[23] = RCAR_GP_PIN(4, 8), /* SCL0 */
[24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */
[25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */
[26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */
[27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
[28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */
[29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */
[30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */
[31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
} },
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
[ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
[ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
[ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */
[ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */
[ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */
[ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */
[ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */
[ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */
[ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */
[ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
[10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
[11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */
[12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */
[13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */
[14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */
[15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */
[16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */
[17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */
[18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */
[19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */
[20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */
[21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */
[22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
[23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */
[24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */
[25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */
[26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */
[27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */
[28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */
[29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */
[30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */
[31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */
} },
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */
[30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */
[31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */
} },
{ /* sentinel */ }
};
enum ioctrl_regs {
TDSELCTRL,
};
@ -2843,8 +3071,83 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
static const struct pinmux_bias_reg *
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *puen_bit, unsigned int *pud_bit)
{
const struct pinmux_bias_reg *reg;
unsigned int bit;
reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
if (!reg)
return reg;
*puen_bit = bit;
/* NFWE# and NFRE# use different bit positions in PUD2 */
switch (pin) {
case RCAR_GP_PIN(3, 0): /* NFRE# */
*pud_bit = 7;
break;
case RCAR_GP_PIN(3, 1): /* NFWE# */
*pud_bit = 8;
break;
default:
*pud_bit = bit;
break;
}
return reg;
}
static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
{
const struct pinmux_bias_reg *reg;
unsigned int puen_bit, pud_bit;
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
if (!reg)
return PIN_CONFIG_BIAS_DISABLE;
if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
return PIN_CONFIG_BIAS_DISABLE;
else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_PULL_DOWN;
}
static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
const struct pinmux_bias_reg *reg;
unsigned int puen_bit, pud_bit;
u32 enable, updown;
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
if (!reg)
return;
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
if (bias != PIN_CONFIG_BIAS_DISABLE) {
enable |= BIT(puen_bit);
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
if (bias == PIN_CONFIG_BIAS_PULL_UP)
updown |= BIT(pud_bit);
sh_pfc_write(pfc, reg->pud, updown);
}
sh_pfc_write(pfc, reg->puen, enable);
}
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
.get_bias = r8a77995_pinmux_get_bias,
.set_bias = r8a77995_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
@ -2862,6 +3165,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,

1175
drivers/pinctrl/renesas/pinctrl-rzg2l.c Normal file
View File

File diff suppressed because it is too large Load Diff

16
drivers/pinctrl/renesas/pinctrl.c
View File

@ -841,7 +841,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
return pinctrl_enable(pmx->pctl);
}
static const struct pinmux_bias_reg *
const struct pinmux_bias_reg *
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit)
{
@ -898,17 +898,17 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
if (reg->puen) {
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
if (bias != PIN_CONFIG_BIAS_DISABLE)
if (bias != PIN_CONFIG_BIAS_DISABLE) {
enable |= BIT(bit);
if (reg->pud) {
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
if (bias == PIN_CONFIG_BIAS_PULL_UP)
updown |= BIT(bit);
if (reg->pud) {
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
if (bias == PIN_CONFIG_BIAS_PULL_UP)
updown |= BIT(bit);
sh_pfc_write(pfc, reg->pud, updown);
sh_pfc_write(pfc, reg->pud, updown);
}
}
sh_pfc_write(pfc, reg->puen, enable);
} else {
enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);

7
drivers/pinctrl/renesas/sh_pfc.h
View File

@ -332,8 +332,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
extern const struct sh_pfc_soc_info r8a77950_pinmux_info;
extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
@ -781,6 +781,9 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
/*
* Bias helpers
*/
const struct pinmux_bias_reg *
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit);
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);

116
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
View File

@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
/*
* Bank type for non-alive type. Bit fields:
* CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
*/
static const struct samsung_pin_bank_type exynos850_bank_type_off = {
.fld_width = { 4, 1, 4, 4, 2, 4, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
};
/*
* Bank type for alive type. Bit fields:
* CON: 4, DAT: 1, PUD: 4, DRV: 4
*/
static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
.fld_width = { 4, 1, 4, 4, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
/* Pad retention control code for accessing PMU regmap */
static atomic_t exynos_shared_retention_refcnt;
@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
.ctrl = exynos7_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
};
/* pin banks of exynos850 pin-controller 0 (ALIVE) */
static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"),
};
/* pin banks of exynos850 pin-controller 1 (CMGP) */
static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c),
EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14),
EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18),
EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c),
};
/* pin banks of exynos850 pin-controller 2 (AUD) */
static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
};
/* pin banks of exynos850 pin-controller 3 (HSI) */
static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
};
/* pin banks of exynos850 pin-controller 4 (CORE) */
static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
};
/* pin banks of exynos850 pin-controller 5 (PERI) */
static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = {
/* Must start with EINTG banks, ordered by EINT group number. */
EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14),
EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18),
EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c),
EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
};
static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 ALIVE data */
.pin_banks = exynos850_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos850_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
}, {
/* pin-controller instance 1 CMGP data */
.pin_banks = exynos850_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos850_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
}, {
/* pin-controller instance 2 AUD data */
.pin_banks = exynos850_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos850_pin_banks2),
}, {
/* pin-controller instance 3 HSI data */
.pin_banks = exynos850_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos850_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
}, {
/* pin-controller instance 4 CORE data */
.pin_banks = exynos850_pin_banks4,
.nr_banks = ARRAY_SIZE(exynos850_pin_banks4),
.eint_gpio_init = exynos_eint_gpio_init,
}, {
/* pin-controller instance 5 PERI data */
.pin_banks = exynos850_pin_banks5,
.nr_banks = ARRAY_SIZE(exynos850_pin_banks5),
.eint_gpio_init = exynos_eint_gpio_init,
},
};
const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
.ctrl = exynos850_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
};

29
drivers/pinctrl/samsung/pinctrl-exynos.h
View File

@ -108,6 +108,35 @@
.pctl_res_idx = pctl_idx, \
} \
#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
{ \
.type = &exynos850_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &exynos850_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \
{ \
.type = &exynos850_bank_type_alive, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_offset = offs, \
.name = id \
}
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.

4
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -918,7 +918,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
pin_bank->grange.pin_base = drvdata->pin_base
+ pin_bank->pin_base;
pin_bank->grange.base = pin_bank->grange.pin_base;
pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
pin_bank->grange.npins = pin_bank->nr_pins;
pin_bank->grange.gc = &pin_bank->gpio_chip;
pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
}
@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynos5433_of_data },
{ .compatible = "samsung,exynos7-pinctrl",
.data = &exynos7_of_data },
{ .compatible = "samsung,exynos850-pinctrl",
.data = &exynos850_of_data },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",

1
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;

6
drivers/pinctrl/stm32/Kconfig
View File

@ -40,6 +40,12 @@ config PINCTRL_STM32H743
default MACH_STM32H743
select PINCTRL_STM32
config PINCTRL_STM32MP135
bool "STMicroelectronics STM32MP135 pin control" if COMPILE_TEST && !MACH_STM32MP13
depends on OF && HAS_IOMEM
default MACH_STM32MP13
select PINCTRL_STM32
config PINCTRL_STM32MP157
bool "STMicroelectronics STM32MP157 pin control" if COMPILE_TEST && !MACH_STM32MP157
depends on OF && HAS_IOMEM

1
drivers/pinctrl/stm32/Makefile
View File

@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_STM32F469) += pinctrl-stm32f469.o
obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o
obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o
obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o
obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o
obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o

1679
drivers/pinctrl/stm32/pinctrl-stm32mp135.c Normal file
View File

File diff suppressed because it is too large Load Diff

0
arch/arm/boot/dts/mt8135-pinfunc.h → include/dt-bindings/pinctrl/mt8135-pinfunc.h
View File

0
arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h → include/dt-bindings/pinctrl/mt8183-pinfunc.h
View File

17
include/dt-bindings/pinctrl/pinctrl-zynq.h Normal file
View File

@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* MIO pin configuration defines for Xilinx Zynq
*
* Copyright (C) 2021 Xilinx, Inc.
*/
#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H
#define _DT_BINDINGS_PINCTRL_ZYNQ_H
/* Configuration options for different power supplies */
#define IO_STANDARD_LVCMOS18 1
#define IO_STANDARD_LVCMOS25 2
#define IO_STANDARD_LVCMOS33 3
#define IO_STANDARD_HSTL 4
#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */

23
include/dt-bindings/pinctrl/rzg2l-pinctrl.h Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for Renesas RZ/G2L family pinctrl bindings.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
#define __DT_BINDINGS_RZG2L_PINCTRL_H
#define RZG2L_PINS_PER_PORT 8
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
/* Convert a port and pin label to its global pin index */
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */