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clk: ingenic: Add .set_rate_hook() for PLL clocks 

The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Aidan MacDonald 2022-10-26 20:43:42 +01:00 committed by Stephen Boyd
parent d84bf9d630
commit c799a77720
2 changed files with 7 additions and 0 deletions
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3
drivers/clk/ingenic/cgu.c
View File

@ -232,6 +232,9 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
writel(ctl, cgu->base + pll_info->reg);
if (pll_info->set_rate_hook)
pll_info->set_rate_hook(pll_info, rate, parent_rate);
/* If the PLL is enabled, verify that it's stable */
if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))
ret = ingenic_pll_check_stable(cgu, pll_info);

4
drivers/clk/ingenic/cgu.h
View File

@ -46,6 +46,8 @@
* -1 if there is no enable bit (ie, the PLL is always on)
* @stable_bit: the index of the stable bit in the PLL control register, or
* -1 if there is no stable bit
* @set_rate_hook: hook called immediately after updating the CGU register,
* before releasing the spinlock
*/
struct ingenic_cgu_pll_info {
unsigned reg;
@ -61,6 +63,8 @@ struct ingenic_cgu_pll_info {
void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
unsigned long rate, unsigned long parent_rate,
unsigned int *m, unsigned int *n, unsigned int *od);
void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,
unsigned long rate, unsigned long parent_rate);
};
/**