diff --git a/MAINTAINERS b/MAINTAINERS index 3bdc260e36b7..395ea06c427d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12189,6 +12189,7 @@ M: Tomasz Figa M: Chanwoo Choi S: Supported L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) +T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git F: drivers/clk/samsung/ F: include/dt-bindings/clock/exynos*.h F: Documentation/devicetree/bindings/clock/exynos*.txt diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index ef8900bc077f..513826393158 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -8,9 +8,11 @@ obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5-subcmu.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5-subcmu.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 5bfc92ee3129..b4b057c7301c 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -143,10 +143,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(dev, res); - if (IS_ERR(reg_base)) { - dev_err(dev, "failed to map audss registers\n"); + if (IS_ERR(reg_base)) return PTR_ERR(reg_base); - } epll = ERR_PTR(-ENODEV); diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 1b81e283f605..27c9d23657b3 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -670,73 +670,73 @@ static const struct samsung_gate_clock gate_clks[] __initconst = { /* APLL & MPLL & BPLL & UPLL */ static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = { - PLL_35XX_RATE(1200000000, 400, 4, 1), - PLL_35XX_RATE(1100000000, 275, 3, 1), - PLL_35XX_RATE(1066000000, 533, 6, 1), - PLL_35XX_RATE(1000000000, 250, 3, 1), - PLL_35XX_RATE( 960000000, 320, 4, 1), - PLL_35XX_RATE( 900000000, 300, 4, 1), - PLL_35XX_RATE( 850000000, 425, 6, 1), - PLL_35XX_RATE( 800000000, 200, 3, 1), - PLL_35XX_RATE( 700000000, 175, 3, 1), - PLL_35XX_RATE( 667000000, 667, 12, 1), - PLL_35XX_RATE( 600000000, 400, 4, 2), - PLL_35XX_RATE( 533000000, 533, 6, 2), - PLL_35XX_RATE( 520000000, 260, 3, 2), - PLL_35XX_RATE( 500000000, 250, 3, 2), - PLL_35XX_RATE( 400000000, 200, 3, 2), - PLL_35XX_RATE( 200000000, 200, 3, 3), - PLL_35XX_RATE( 100000000, 200, 3, 4), + PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1), + PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), + PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1), + PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), + PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1), + PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1), + PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1), + PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), + PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), + PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1), + PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2), + PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2), + PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2), + PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), + PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), + PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), + PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4), { /* sentinel */ } }; /* EPLL */ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = { - PLL_36XX_RATE(800000000, 200, 3, 1, 0), - PLL_36XX_RATE(288000000, 96, 2, 2, 0), - PLL_36XX_RATE(192000000, 128, 2, 3, 0), - PLL_36XX_RATE(144000000, 96, 2, 3, 0), - PLL_36XX_RATE( 96000000, 128, 2, 4, 0), - PLL_36XX_RATE( 84000000, 112, 2, 4, 0), - PLL_36XX_RATE( 80000004, 106, 2, 4, 43691), - PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), - PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), - PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), - PLL_36XX_RATE( 50000000, 200, 3, 5, 0), - PLL_36XX_RATE( 49152002, 131, 2, 5, 4719), - PLL_36XX_RATE( 48000000, 128, 2, 5, 0), - PLL_36XX_RATE( 45158401, 180, 3, 5, 41524), + PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0), + PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0), + PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0), + PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0), + PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0), + PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691), + PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285), + PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982), + PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0), + PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719), + PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0), + PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524), { /* sentinel */ } }; /* VPLL */ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = { - PLL_36XX_RATE(600000000, 100, 2, 1, 0), - PLL_36XX_RATE(533000000, 266, 3, 2, 32768), - PLL_36XX_RATE(519230987, 173, 2, 2, 5046), - PLL_36XX_RATE(500000000, 250, 3, 2, 0), - PLL_36XX_RATE(445500000, 148, 2, 2, 32768), - PLL_36XX_RATE(445055007, 148, 2, 2, 23047), - PLL_36XX_RATE(400000000, 200, 3, 2, 0), - PLL_36XX_RATE(371250000, 123, 2, 2, 49152), - PLL_36XX_RATE(370878997, 185, 3, 2, 28803), - PLL_36XX_RATE(340000000, 170, 3, 2, 0), - PLL_36XX_RATE(335000015, 111, 2, 2, 43691), - PLL_36XX_RATE(333000000, 111, 2, 2, 0), - PLL_36XX_RATE(330000000, 110, 2, 2, 0), - PLL_36XX_RATE(320000015, 106, 2, 2, 43691), - PLL_36XX_RATE(300000000, 100, 2, 2, 0), - PLL_36XX_RATE(275000000, 275, 3, 3, 0), - PLL_36XX_RATE(222750000, 148, 2, 3, 32768), - PLL_36XX_RATE(222528007, 148, 2, 3, 23069), - PLL_36XX_RATE(160000000, 160, 3, 3, 0), - PLL_36XX_RATE(148500000, 99, 2, 3, 0), - PLL_36XX_RATE(148352005, 98, 2, 3, 59070), - PLL_36XX_RATE(108000000, 144, 2, 4, 0), - PLL_36XX_RATE( 74250000, 99, 2, 4, 0), - PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), - PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), - PLL_36XX_RATE( 54000000, 144, 2, 5, 0), + PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0), + PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768), + PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046), + PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768), + PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047), + PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152), + PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803), + PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691), + PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691), + PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768), + PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069), + PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0), + PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070), + PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0), + PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0), + PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070), + PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156), + PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0), { /* sentinel */ } }; diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 134f25f2a913..0421960eb963 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1266,77 +1266,78 @@ static const struct of_device_id ext_clk_match[] __initconst = { /* PLLs PMS values */ static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = { - PLL_45XX_RATE(1200000000, 150, 3, 1, 28), - PLL_45XX_RATE(1000000000, 250, 6, 1, 28), - PLL_45XX_RATE( 800000000, 200, 6, 1, 28), - PLL_45XX_RATE( 666857142, 389, 14, 1, 13), - PLL_45XX_RATE( 600000000, 100, 4, 1, 13), - PLL_45XX_RATE( 533000000, 533, 24, 1, 5), - PLL_45XX_RATE( 500000000, 250, 6, 2, 28), - PLL_45XX_RATE( 400000000, 200, 6, 2, 28), - PLL_45XX_RATE( 200000000, 200, 6, 3, 28), + PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28), + PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28), + PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28), + PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13), + PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13), + PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5), + PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28), + PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28), + PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28), { /* sentinel */ } }; static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = { - PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), - PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), - PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), - PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), - PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), - PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), - PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), + PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0), + PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0), + PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0), + PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1), + PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1), + PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0), + PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0), { /* sentinel */ } }; static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = { - PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), - PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), - PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), - PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), - PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), + PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0), + PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1), + PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1), + PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0), + PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0), { /* sentinel */ } }; static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { - PLL_35XX_RATE(1704000000, 213, 3, 0), - PLL_35XX_RATE(1600000000, 200, 3, 0), - PLL_35XX_RATE(1500000000, 250, 4, 0), - PLL_35XX_RATE(1400000000, 175, 3, 0), - PLL_35XX_RATE(1300000000, 325, 6, 0), - PLL_35XX_RATE(1200000000, 200, 4, 0), - PLL_35XX_RATE(1100000000, 275, 6, 0), - PLL_35XX_RATE(1000000000, 125, 3, 0), - PLL_35XX_RATE( 900000000, 150, 4, 0), - PLL_35XX_RATE( 800000000, 100, 3, 0), - PLL_35XX_RATE( 700000000, 175, 3, 1), - PLL_35XX_RATE( 600000000, 200, 4, 1), - PLL_35XX_RATE( 500000000, 125, 3, 1), - PLL_35XX_RATE( 400000000, 100, 3, 1), - PLL_35XX_RATE( 300000000, 200, 4, 2), - PLL_35XX_RATE( 200000000, 100, 3, 2), + PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0), + PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0), + PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0), + PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), + PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1), + PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1), + PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1), + PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2), + PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2), { /* sentinel */ } }; static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { - PLL_36XX_RATE(192000000, 48, 3, 1, 0), - PLL_36XX_RATE(180633605, 45, 3, 1, 10381), - PLL_36XX_RATE(180000000, 45, 3, 1, 0), - PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), - PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), - PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), - PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), + PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690), + PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0), + PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381), + PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0), + PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710), + PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762), + PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961), + PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381), { /* sentinel */ } }; static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = { - PLL_36XX_RATE(533000000, 133, 3, 1, 16384), - PLL_36XX_RATE(440000000, 110, 3, 1, 0), - PLL_36XX_RATE(350000000, 175, 3, 2, 0), - PLL_36XX_RATE(266000000, 133, 3, 2, 0), - PLL_36XX_RATE(160000000, 160, 3, 3, 0), - PLL_36XX_RATE(106031250, 53, 3, 2, 1024), - PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), + PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384), + PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0), + PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024), + PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024), { /* sentinel */ } }; diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c new file mode 100644 index 000000000000..93306283d764 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2018 Samsung Electronics Co., Ltd. +// Author: Marek Szyprowski +// Common Clock Framework support for Exynos5 power-domain dependent clocks + +#include +#include +#include +#include + +#include "clk.h" +#include "clk-exynos5-subcmu.h" + +static struct samsung_clk_provider *ctx; +static const struct exynos5_subcmu_info *cmu; +static int nr_cmus; + +static void exynos5_subcmu_clk_save(void __iomem *base, + struct exynos5_subcmu_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) { + rd->save = readl(base + rd->offset); + writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); + rd->save &= rd->mask; + } +}; + +static void exynos5_subcmu_clk_restore(void __iomem *base, + struct exynos5_subcmu_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + writel((readl(base + rd->offset) & ~rd->mask) | rd->save, + base + rd->offset); +} + +static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx, + const struct samsung_gate_clock *list, int nr_clk) +{ + while (nr_clk--) + samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id); +} + +/* + * Pass the needed clock provider context and register sub-CMU clocks + * + * NOTE: This function has to be called from the main, OF_CLK_DECLARE- + * initialized clock provider driver. This happens very early during boot + * process. Then this driver, during core_initcall registers two platform + * drivers: one which binds to the same device-tree node as OF_CLK_DECLARE + * driver and second, for handling its per-domain child-devices. Those + * platform drivers are bound to their devices a bit later in arch_initcall, + * when OF-core populates all device-tree nodes. + */ +void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus, + const struct exynos5_subcmu_info *_cmu) +{ + ctx = _ctx; + cmu = _cmu; + nr_cmus = _nr_cmus; + + for (; _nr_cmus--; _cmu++) { + exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks, + _cmu->nr_gate_clks); + exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs, + _cmu->nr_suspend_regs); + } +} + +static int __maybe_unused exynos5_subcmu_suspend(struct device *dev) +{ + struct exynos5_subcmu_info *info = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs, + info->nr_suspend_regs); + spin_unlock_irqrestore(&ctx->lock, flags); + + return 0; +} + +static int __maybe_unused exynos5_subcmu_resume(struct device *dev) +{ + struct exynos5_subcmu_info *info = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs, + info->nr_suspend_regs); + spin_unlock_irqrestore(&ctx->lock, flags); + + return 0; +} + +static int __init exynos5_subcmu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos5_subcmu_info *info = dev_get_drvdata(dev); + + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + pm_runtime_get(dev); + + ctx->dev = dev; + samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks); + samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks); + ctx->dev = NULL; + + pm_runtime_put_sync(dev); + + return 0; +} + +static const struct dev_pm_ops exynos5_subcmu_pm_ops = { + SET_RUNTIME_PM_OPS(exynos5_subcmu_suspend, + exynos5_subcmu_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver exynos5_subcmu_driver __refdata = { + .driver = { + .name = "exynos5-subcmu", + .suppress_bind_attrs = true, + .pm = &exynos5_subcmu_pm_ops, + }, + .probe = exynos5_subcmu_probe, +}; + +static int __init exynos5_clk_register_subcmu(struct device *parent, + const struct exynos5_subcmu_info *info, + struct device_node *pd_node) +{ + struct of_phandle_args genpdspec = { .np = pd_node }; + struct platform_device *pdev; + + pdev = platform_device_alloc(info->pd_name, -1); + pdev->dev.parent = parent; + pdev->driver_override = "exynos5-subcmu"; + platform_set_drvdata(pdev, (void *)info); + of_genpd_add_device(&genpdspec, &pdev->dev); + platform_device_add(pdev); + + return 0; +} + +static int __init exynos5_clk_probe(struct platform_device *pdev) +{ + struct device_node *np; + const char *name; + int i; + + for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { + if (of_property_read_string(np, "label", &name) < 0) + continue; + for (i = 0; i < nr_cmus; i++) + if (strcmp(cmu[i].pd_name, name) == 0) + exynos5_clk_register_subcmu(&pdev->dev, + &cmu[i], np); + } + return 0; +} + +static const struct of_device_id exynos5_clk_of_match[] = { + { .compatible = "samsung,exynos5250-clock", }, + { .compatible = "samsung,exynos5420-clock", }, + { .compatible = "samsung,exynos5800-clock", }, + { }, +}; + +static struct platform_driver exynos5_clk_driver __refdata = { + .driver = { + .name = "exynos5-clock", + .of_match_table = exynos5_clk_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos5_clk_probe, +}; + +static int __init exynos5_clk_drv_init(void) +{ + platform_driver_register(&exynos5_clk_driver); + platform_driver_register(&exynos5_subcmu_driver); + return 0; +} +core_initcall(exynos5_clk_drv_init); diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.h b/drivers/clk/samsung/clk-exynos5-subcmu.h new file mode 100644 index 000000000000..755ee8aaa3de --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5-subcmu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __CLK_EXYNOS5_SUBCMU_H +#define __CLK_EXYNOS5_SUBCMU_H + +struct exynos5_subcmu_reg_dump { + u32 offset; + u32 value; + u32 mask; + u32 save; +}; + +struct exynos5_subcmu_info { + const struct samsung_div_clock *div_clks; + unsigned int nr_div_clks; + const struct samsung_gate_clock *gate_clks; + unsigned int nr_gate_clks; + struct exynos5_subcmu_reg_dump *suspend_regs; + unsigned int nr_suspend_regs; + const char *pd_name; +}; + +void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus, + const struct exynos5_subcmu_info *cmu); + +#endif diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 9b073c98a891..347fd80c351b 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -18,6 +18,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -560,6 +561,8 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { 0), GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 0), + GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 4, 0, 0), GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub", @@ -570,18 +573,11 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE_IP_GSCL, 9, 0, 0), GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 10, 0, 0), + GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 11, 0, 0), + GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 12, 0, 0), - GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, - 0), - GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, - 0), - GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, - 0), - GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, - 0), - GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, - 0), GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, @@ -671,10 +667,6 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), - GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", - GATE_IP_DISP1, 9, 0, 0), - GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", - GATE_IP_DISP1, 8, 0, 0), GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0), GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub", GATE_IP_ISP0, 8, 0, 0), @@ -698,48 +690,80 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE_IP_ISP1, 7, 0, 0), }; +static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, + 0), + GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, + 0), + GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, + 0), + GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, + 0), + GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, + 0), + GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 9, 0, 0), + GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 8, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */ + { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */ +}; + +static const struct exynos5_subcmu_info exynos5250_disp_subcmu = { + .gate_clks = exynos5250_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks), + .suspend_regs = exynos5250_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs), + .pd_name = "DISP1", +}; + static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ - PLL_36XX_RATE(266000000, 266, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0), /* Not in UM, but need for eDP on snow */ - PLL_36XX_RATE(70500000, 94, 2, 4, 0), + PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0), { }, }; static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ - PLL_36XX_RATE(192000000, 64, 2, 2, 0), - PLL_36XX_RATE(180633600, 90, 3, 2, 20762), - PLL_36XX_RATE(180000000, 90, 3, 2, 0), - PLL_36XX_RATE(73728000, 98, 2, 4, 19923), - PLL_36XX_RATE(67737600, 90, 2, 4, 20762), - PLL_36XX_RATE(49152000, 98, 3, 4, 19923), - PLL_36XX_RATE(45158400, 90, 3, 4, 20762), - PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762), + PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762), + PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762), + PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719), { }, }; static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = { /* sorted in descending order */ - /* PLL_35XX_RATE(rate, m, p, s) */ - PLL_35XX_RATE(1700000000, 425, 6, 0), - PLL_35XX_RATE(1600000000, 200, 3, 0), - PLL_35XX_RATE(1500000000, 250, 4, 0), - PLL_35XX_RATE(1400000000, 175, 3, 0), - PLL_35XX_RATE(1300000000, 325, 6, 0), - PLL_35XX_RATE(1200000000, 200, 4, 0), - PLL_35XX_RATE(1100000000, 275, 6, 0), - PLL_35XX_RATE(1000000000, 125, 3, 0), - PLL_35XX_RATE(900000000, 150, 4, 0), - PLL_35XX_RATE(800000000, 100, 3, 0), - PLL_35XX_RATE(700000000, 175, 3, 1), - PLL_35XX_RATE(600000000, 200, 4, 1), - PLL_35XX_RATE(500000000, 125, 3, 1), - PLL_35XX_RATE(400000000, 100, 3, 1), - PLL_35XX_RATE(300000000, 200, 4, 2), - PLL_35XX_RATE(200000000, 100, 3, 2), + /* PLL_35XX_RATE(fin, rate, m, p, s) */ + PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0), + PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0), + PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0), + PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), + PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1), + PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1), + PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1), + PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2), + PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2), }; static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { @@ -859,10 +883,11 @@ static void __init exynos5250_clk_init(struct device_node *np) __raw_writel(tmp, reg_base + PWR_CTRL2); exynos5250_clk_sleep_init(); + exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); samsung_clk_of_add_provider(np, ctx); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", _get_rate("div_arm2")); } -CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index fd1d9bfc151b..2cc2583abd87 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -23,57 +23,57 @@ * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. */ static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = { - PLL_35XX_RATE(1700000000, 425, 6, 0), - PLL_35XX_RATE(1600000000, 200, 3, 0), - PLL_35XX_RATE(1500000000, 250, 4, 0), - PLL_35XX_RATE(1400000000, 175, 3, 0), - PLL_35XX_RATE(1300000000, 325, 6, 0), - PLL_35XX_RATE(1200000000, 400, 4, 1), - PLL_35XX_RATE(1100000000, 275, 3, 1), - PLL_35XX_RATE(1000000000, 250, 3, 1), - PLL_35XX_RATE(933000000, 311, 4, 1), - PLL_35XX_RATE(900000000, 300, 4, 1), - PLL_35XX_RATE(800000000, 200, 3, 1), - PLL_35XX_RATE(733000000, 733, 12, 1), - PLL_35XX_RATE(700000000, 175, 3, 1), - PLL_35XX_RATE(667000000, 667, 12, 1), - PLL_35XX_RATE(633000000, 211, 4, 1), - PLL_35XX_RATE(620000000, 310, 3, 2), - PLL_35XX_RATE(600000000, 400, 4, 2), - PLL_35XX_RATE(543000000, 362, 4, 2), - PLL_35XX_RATE(533000000, 533, 6, 2), - PLL_35XX_RATE(500000000, 250, 3, 2), - PLL_35XX_RATE(450000000, 300, 4, 2), - PLL_35XX_RATE(400000000, 200, 3, 2), - PLL_35XX_RATE(350000000, 175, 3, 2), - PLL_35XX_RATE(300000000, 400, 4, 3), - PLL_35XX_RATE(266000000, 266, 3, 3), - PLL_35XX_RATE(200000000, 200, 3, 3), - PLL_35XX_RATE(160000000, 160, 3, 3), + PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1), + PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), + PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), + PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1), + PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1), + PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), + PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1), + PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), + PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2), + PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2), + PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2), + PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2), + PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), + PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2), + PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), + PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2), + PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3), + PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3), + PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), + PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3), }; /* * Applicable for 2650 Type PLL for AUD_PLL. */ static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { - PLL_36XX_RATE(1600000000, 200, 3, 0, 0), - PLL_36XX_RATE(1200000000, 100, 2, 0, 0), - PLL_36XX_RATE(1000000000, 250, 3, 1, 0), - PLL_36XX_RATE(800000000, 200, 3, 1, 0), - PLL_36XX_RATE(600000000, 100, 2, 1, 0), - PLL_36XX_RATE(532000000, 266, 3, 2, 0), - PLL_36XX_RATE(480000000, 160, 2, 2, 0), - PLL_36XX_RATE(432000000, 144, 2, 2, 0), - PLL_36XX_RATE(400000000, 200, 3, 2, 0), - PLL_36XX_RATE(394073130, 459, 7, 2, 49282), - PLL_36XX_RATE(333000000, 111, 2, 2, 0), - PLL_36XX_RATE(300000000, 100, 2, 2, 0), - PLL_36XX_RATE(266000000, 266, 3, 3, 0), - PLL_36XX_RATE(200000000, 200, 3, 3, 0), - PLL_36XX_RATE(166000000, 166, 3, 3, 0), - PLL_36XX_RATE(133000000, 266, 3, 4, 0), - PLL_36XX_RATE(100000000, 200, 3, 4, 0), - PLL_36XX_RATE(66000000, 176, 2, 5, 0), + PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0), + PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0), + PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0), + PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0), + PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0), + PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282), + PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0), + PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0), + PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0), }; /* CMU_AUD */ diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index fc471a49e8f4..0a0b09591e6f 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -226,16 +226,16 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { }; static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = { - PLL_36XX_RATE(400000000U, 200, 3, 2, 0), - PLL_36XX_RATE(333000000U, 111, 2, 2, 0), - PLL_36XX_RATE(300000000U, 100, 2, 2, 0), - PLL_36XX_RATE(266000000U, 266, 3, 3, 0), - PLL_36XX_RATE(200000000U, 200, 3, 3, 0), - PLL_36XX_RATE(192000000U, 192, 3, 3, 0), - PLL_36XX_RATE(166000000U, 166, 3, 3, 0), - PLL_36XX_RATE(133000000U, 266, 3, 4, 0), - PLL_36XX_RATE(100000000U, 200, 3, 4, 0), - PLL_36XX_RATE(66000000U, 176, 2, 5, 0), + PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0), + PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), + PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0), }; static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = { diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 45d34f601e9e..95e1bf69449b 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -19,6 +19,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -620,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", mout_group5_5800_p, SRC_TOP7, 16, 2), - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), + MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), }; @@ -863,7 +865,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), - DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), @@ -912,8 +913,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), - /* Mfc Block */ - DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), /* PCM */ DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), @@ -932,8 +931,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), /* GSCL Block */ - DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", - DIV2_RATIO0, 4, 2), DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), /* MSCL Block */ @@ -1190,8 +1187,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", GATE_TOP_SCLK_GSCL, 7, 0, 0), - GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), - GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", GATE_IP_GSCL0, 4, 0, 0), GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", @@ -1205,10 +1200,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_IP_GSCL1, 3, 0, 0), GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", GATE_IP_GSCL1, 4, 0, 0), - GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", - GATE_IP_GSCL1, 6, 0, 0), - GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", - GATE_IP_GSCL1, 7, 0, 0), GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", @@ -1227,18 +1218,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", GATE_IP_MSCL, 10, 0, 0), - GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), - GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), - GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), - GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), - GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", - GATE_IP_DISP1, 7, 0, 0), - GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", - GATE_IP_DISP1, 8, 0, 0), - GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", - GATE_IP_DISP1, 9, 0, 0), - /* ISP */ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), @@ -1255,48 +1234,138 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), - GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), - GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), - GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), - GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), }; +static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { + DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), +}; + +static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), + GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), + GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), + GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), + GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", + GATE_IP_DISP1, 7, 0, 0), + GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", + GATE_IP_DISP1, 8, 0, 0), + GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", + GATE_IP_DISP1, 9, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ + { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ + { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ + { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ +}; + +static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { + DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", + DIV2_RATIO0, 4, 2), +}; + +static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { + GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), + GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), + GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", + GATE_IP_GSCL1, 6, 0, 0), + GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", + GATE_IP_GSCL1, 7, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { + { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ + { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ + { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ + { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ +}; + +static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { + DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), +}; + +static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { + GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), + GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), + GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { + { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ + { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ + { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ +}; + +static const struct exynos5_subcmu_info exynos5x_subcmus[] = { + { + .div_clks = exynos5x_disp_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), + .gate_clks = exynos5x_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), + .suspend_regs = exynos5x_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), + .pd_name = "DISP", + }, { + .div_clks = exynos5x_gsc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), + .gate_clks = exynos5x_gsc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), + .suspend_regs = exynos5x_gsc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), + .pd_name = "GSC", + }, { + .div_clks = exynos5x_mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), + .gate_clks = exynos5x_mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), + .suspend_regs = exynos5x_mfc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), + .pd_name = "MFC", + }, +}; + static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { - PLL_35XX_RATE(2000000000, 250, 3, 0), - PLL_35XX_RATE(1900000000, 475, 6, 0), - PLL_35XX_RATE(1800000000, 225, 3, 0), - PLL_35XX_RATE(1700000000, 425, 6, 0), - PLL_35XX_RATE(1600000000, 200, 3, 0), - PLL_35XX_RATE(1500000000, 250, 4, 0), - PLL_35XX_RATE(1400000000, 175, 3, 0), - PLL_35XX_RATE(1300000000, 325, 6, 0), - PLL_35XX_RATE(1200000000, 200, 2, 1), - PLL_35XX_RATE(1100000000, 275, 3, 1), - PLL_35XX_RATE(1000000000, 250, 3, 1), - PLL_35XX_RATE(900000000, 150, 2, 1), - PLL_35XX_RATE(800000000, 200, 3, 1), - PLL_35XX_RATE(700000000, 175, 3, 1), - PLL_35XX_RATE(600000000, 200, 2, 2), - PLL_35XX_RATE(500000000, 250, 3, 2), - PLL_35XX_RATE(400000000, 200, 3, 2), - PLL_35XX_RATE(300000000, 200, 2, 3), - PLL_35XX_RATE(200000000, 200, 3, 3), + PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), + PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), + PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), + PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), + PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), + PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), + PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), + PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), + PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), + PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), + PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), + PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { - PLL_36XX_RATE(600000000U, 100, 2, 1, 0), - PLL_36XX_RATE(400000000U, 200, 3, 2, 0), - PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), - PLL_36XX_RATE(361267218U, 301, 5, 2, 3671), - PLL_36XX_RATE(200000000U, 200, 3, 3, 0), - PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), - PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), - PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), - PLL_36XX_RATE(100000000U, 200, 3, 4, 0), - PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), - PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), - PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), + PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), + PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), + PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), + PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), + PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), + PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), + PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), + PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), + PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), + PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), + PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), + PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), + PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), + PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), }; static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { @@ -1472,6 +1541,8 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); exynos5420_clk_sleep_init(); + exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), + exynos5x_subcmus); samsung_clk_of_add_provider(np, ctx); } @@ -1480,10 +1551,12 @@ static void __init exynos5420_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5420); } -CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", + exynos5420_clk_init); static void __init exynos5800_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5800); } -CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", + exynos5800_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index db270908037a..5305ace514b2 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -703,68 +703,69 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { - PLL_35XX_RATE(2500000000U, 625, 6, 0), - PLL_35XX_RATE(2400000000U, 500, 5, 0), - PLL_35XX_RATE(2300000000U, 575, 6, 0), - PLL_35XX_RATE(2200000000U, 550, 6, 0), - PLL_35XX_RATE(2100000000U, 350, 4, 0), - PLL_35XX_RATE(2000000000U, 500, 6, 0), - PLL_35XX_RATE(1900000000U, 475, 6, 0), - PLL_35XX_RATE(1800000000U, 375, 5, 0), - PLL_35XX_RATE(1700000000U, 425, 6, 0), - PLL_35XX_RATE(1600000000U, 400, 6, 0), - PLL_35XX_RATE(1500000000U, 250, 4, 0), - PLL_35XX_RATE(1400000000U, 350, 6, 0), - PLL_35XX_RATE(1332000000U, 222, 4, 0), - PLL_35XX_RATE(1300000000U, 325, 6, 0), - PLL_35XX_RATE(1200000000U, 500, 5, 1), - PLL_35XX_RATE(1100000000U, 550, 6, 1), - PLL_35XX_RATE(1086000000U, 362, 4, 1), - PLL_35XX_RATE(1066000000U, 533, 6, 1), - PLL_35XX_RATE(1000000000U, 500, 6, 1), - PLL_35XX_RATE(933000000U, 311, 4, 1), - PLL_35XX_RATE(921000000U, 307, 4, 1), - PLL_35XX_RATE(900000000U, 375, 5, 1), - PLL_35XX_RATE(825000000U, 275, 4, 1), - PLL_35XX_RATE(800000000U, 400, 6, 1), - PLL_35XX_RATE(733000000U, 733, 12, 1), - PLL_35XX_RATE(700000000U, 175, 3, 1), - PLL_35XX_RATE(667000000U, 222, 4, 1), - PLL_35XX_RATE(633000000U, 211, 4, 1), - PLL_35XX_RATE(600000000U, 500, 5, 2), - PLL_35XX_RATE(552000000U, 460, 5, 2), - PLL_35XX_RATE(550000000U, 550, 6, 2), - PLL_35XX_RATE(543000000U, 362, 4, 2), - PLL_35XX_RATE(533000000U, 533, 6, 2), - PLL_35XX_RATE(500000000U, 500, 6, 2), - PLL_35XX_RATE(444000000U, 370, 5, 2), - PLL_35XX_RATE(420000000U, 350, 5, 2), - PLL_35XX_RATE(400000000U, 400, 6, 2), - PLL_35XX_RATE(350000000U, 350, 6, 2), - PLL_35XX_RATE(333000000U, 222, 4, 2), - PLL_35XX_RATE(300000000U, 500, 5, 3), - PLL_35XX_RATE(278000000U, 556, 6, 3), - PLL_35XX_RATE(266000000U, 532, 6, 3), - PLL_35XX_RATE(250000000U, 500, 6, 3), - PLL_35XX_RATE(200000000U, 400, 6, 3), - PLL_35XX_RATE(166000000U, 332, 6, 3), - PLL_35XX_RATE(160000000U, 320, 6, 3), - PLL_35XX_RATE(133000000U, 532, 6, 4), - PLL_35XX_RATE(100000000U, 400, 6, 4), + PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0), + PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0), + PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0), + PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0), + PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0), + PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0), + PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0), + PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0), + PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1), + PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1), + PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1), + PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1), + PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1), + PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1), + PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1), + PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1), + PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1), + PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1), + PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1), + PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1), + PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2), + PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2), + PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2), + PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2), + PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2), + PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2), + PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2), + PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2), + PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2), + PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2), + PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2), + PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3), + PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3), + PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3), + PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3), + PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3), + PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3), + PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3), + PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4), + PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4), { /* sentinel */ } }; /* AUD_PLL */ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { - PLL_36XX_RATE(400000000U, 200, 3, 2, 0), - PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), - PLL_36XX_RATE(384000000U, 128, 2, 2, 0), - PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), - PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), - PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), - PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), - PLL_36XX_RATE(288000000U, 96, 1, 3, 0), - PLL_36XX_RATE(252000000U, 84, 1, 3, 0), + PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), + PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), + PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0), + PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729), + PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148), + PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816), + PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923), + PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0), + PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0), + PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), { /* sentinel */ } }; @@ -1672,7 +1673,7 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = { ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, - CLK_SET_RATE_PARENT, 0), + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", @@ -5513,10 +5514,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(dev, res); - if (IS_ERR(reg_base)) { - dev_err(dev, "failed to map registers\n"); + if (IS_ERR(reg_base)) return PTR_ERR(reg_base); - } for (i = 0; i < info->nr_clk_ids; ++i) ctx->clk_data.hws[i] = ERR_PTR(-ENOENT); diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 5931a4140c3d..492d51691080 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = { }; static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { - PLL_36XX_RATE(491520000, 20, 1, 0, 31457), + PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457), {}, }; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 61eb8abbfd9c..ca57b3dfa814 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -41,35 +41,62 @@ enum samsung_pll_type { pll_1460x, }; -#define PLL_35XX_RATE(_rate, _m, _p, _s) \ +#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ + ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s))) +#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \ + BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout))) + +#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ { \ - .rate = (_rate), \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + _m, _p, _s, 0, 16), \ .mdiv = (_m), \ .pdiv = (_p), \ .sdiv = (_s), \ } -#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \ +#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \ { \ - .rate = (_rate), \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + _m + 8, _p + 2, _s, 0, 16), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \ + { \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + 2 * (_m + 8), _p + 2, _s, 0, 16), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \ + { \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + _m, _p, _s, _k, 16), \ .mdiv = (_m), \ .pdiv = (_p), \ .sdiv = (_s), \ .kdiv = (_k), \ } -#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \ +#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \ { \ - .rate = (_rate), \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + _m, _p, _s - 1, 0, 16), \ .mdiv = (_m), \ .pdiv = (_p), \ .sdiv = (_s), \ .afc = (_afc), \ } -#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \ +#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \ { \ - .rate = (_rate), \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + _m, _p, _s, _k, 16), \ .mdiv = (_m), \ .pdiv = (_p), \ .sdiv = (_s), \ @@ -77,9 +104,10 @@ enum samsung_pll_type { .vsel = (_vsel), \ } -#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ +#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ { \ - .rate = (_rate), \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + _m, _p, _s, _k, 10), \ .mdiv = (_m), \ .pdiv = (_p), \ .sdiv = (_s), \ diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c index e0650c33863b..0c6aa3e51336 100644 --- a/drivers/clk/samsung/clk-s3c2410.c +++ b/drivers/clk/samsung/clk-s3c2410.c @@ -162,34 +162,34 @@ struct samsung_clock_alias s3c2410_common_aliases[] __initdata = { static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = { /* sorted in descending order */ /* 2410A extras */ - PLL_35XX_RATE(270000000, 127, 1, 1), - PLL_35XX_RATE(268000000, 126, 1, 1), - PLL_35XX_RATE(266000000, 125, 1, 1), - PLL_35XX_RATE(226000000, 105, 1, 1), - PLL_35XX_RATE(210000000, 132, 2, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1), /* 2410 common */ - PLL_35XX_RATE(203000000, 161, 3, 1), - PLL_35XX_RATE(192000000, 88, 1, 1), - PLL_35XX_RATE(186000000, 85, 1, 1), - PLL_35XX_RATE(180000000, 82, 1, 1), - PLL_35XX_RATE(170000000, 77, 1, 1), - PLL_35XX_RATE(158000000, 71, 1, 1), - PLL_35XX_RATE(152000000, 68, 1, 1), - PLL_35XX_RATE(147000000, 90, 2, 1), - PLL_35XX_RATE(135000000, 82, 2, 1), - PLL_35XX_RATE(124000000, 116, 1, 2), - PLL_35XX_RATE(118000000, 150, 2, 2), - PLL_35XX_RATE(113000000, 105, 1, 2), - PLL_35XX_RATE(101000000, 127, 2, 2), - PLL_35XX_RATE(90000000, 112, 2, 2), - PLL_35XX_RATE(85000000, 105, 2, 2), - PLL_35XX_RATE(79000000, 71, 1, 2), - PLL_35XX_RATE(68000000, 82, 2, 2), - PLL_35XX_RATE(56000000, 142, 2, 3), - PLL_35XX_RATE(48000000, 120, 2, 3), - PLL_35XX_RATE(51000000, 161, 3, 3), - PLL_35XX_RATE(45000000, 82, 1, 3), - PLL_35XX_RATE(34000000, 82, 2, 3), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3), + PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3), { /* sentinel */ }, }; @@ -229,33 +229,33 @@ struct samsung_clock_alias s3c2410_aliases[] __initdata = { static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = { /* sorted in descending order */ - PLL_35XX_RATE(400000000, 0x5c, 1, 1), - PLL_35XX_RATE(390000000, 0x7a, 2, 1), - PLL_35XX_RATE(380000000, 0x57, 1, 1), - PLL_35XX_RATE(370000000, 0xb1, 4, 1), - PLL_35XX_RATE(360000000, 0x70, 2, 1), - PLL_35XX_RATE(350000000, 0xa7, 4, 1), - PLL_35XX_RATE(340000000, 0x4d, 1, 1), - PLL_35XX_RATE(330000000, 0x66, 2, 1), - PLL_35XX_RATE(320000000, 0x98, 4, 1), - PLL_35XX_RATE(310000000, 0x93, 4, 1), - PLL_35XX_RATE(300000000, 0x75, 3, 1), - PLL_35XX_RATE(240000000, 0x70, 1, 2), - PLL_35XX_RATE(230000000, 0x6b, 1, 2), - PLL_35XX_RATE(220000000, 0x66, 1, 2), - PLL_35XX_RATE(210000000, 0x84, 2, 2), - PLL_35XX_RATE(200000000, 0x5c, 1, 2), - PLL_35XX_RATE(190000000, 0x57, 1, 2), - PLL_35XX_RATE(180000000, 0x70, 2, 2), - PLL_35XX_RATE(170000000, 0x4d, 1, 2), - PLL_35XX_RATE(160000000, 0x98, 4, 2), - PLL_35XX_RATE(150000000, 0x75, 3, 2), - PLL_35XX_RATE(120000000, 0x70, 1, 3), - PLL_35XX_RATE(110000000, 0x66, 1, 3), - PLL_35XX_RATE(100000000, 0x5c, 1, 3), - PLL_35XX_RATE(90000000, 0x70, 2, 3), - PLL_35XX_RATE(80000000, 0x98, 4, 3), - PLL_35XX_RATE(75000000, 0x75, 3, 3), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3), + PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3), { /* sentinel */ }, }; diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c index b8340a49921b..1555e407529e 100644 --- a/drivers/clk/samsung/clk-s3c2412.c +++ b/drivers/clk/samsung/clk-s3c2412.c @@ -27,11 +27,6 @@ #define CLKSRC 0x1c #define SWRST 0x30 -/* list of PLLs to be registered */ -enum s3c2412_plls { - mpll, upll, -}; - static void __iomem *reg_base; #ifdef CONFIG_PM_SLEEP @@ -144,10 +139,8 @@ struct samsung_mux_clock s3c2412_muxes[] __initdata = { }; static struct samsung_pll_clock s3c2412_plls[] __initdata = { - [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", - LOCKTIME, MPLLCON, NULL), - [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", - LOCKTIME, UPLLCON, NULL), + PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL), + PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL), }; struct samsung_gate_clock s3c2412_gates[] __initdata = { diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c index d94b85a42356..9580a6baf4d7 100644 --- a/drivers/clk/samsung/clk-s3c2443.c +++ b/drivers/clk/samsung/clk-s3c2443.c @@ -41,11 +41,6 @@ enum supported_socs { S3C2450, }; -/* list of PLLs to be registered */ -enum s3c2443_plls { - mpll, epll, -}; - static void __iomem *reg_base; #ifdef CONFIG_PM_SLEEP @@ -225,10 +220,8 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { /* S3C2416 specific clocks */ static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { - [mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", - LOCKCON0, MPLLCON, NULL), - [epll] = PLL(pll_6553, EPLL, "epll", "epllref", - LOCKCON1, EPLLCON, NULL), + PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL), + PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL), }; PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" }; @@ -279,10 +272,8 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = { /* S3C2443 specific clocks */ static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = { - [mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref", - LOCKCON0, MPLLCON, NULL), - [epll] = PLL(pll_2126, EPLL, "epll", "epllref", - LOCKCON1, EPLLCON, NULL), + PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL), + PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL), }; static struct clk_div_table armdiv_s3c2443_d[] = { diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index 7306867a0ab8..6db01cf5ab83 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -56,11 +56,6 @@ #define GATE_ON(_id, cname, pname, o, b) \ GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0) -/* list of PLLs to be registered */ -enum s3c64xx_plls { - apll, mpll, epll, -}; - static void __iomem *reg_base; static bool is_s3c6400; @@ -364,12 +359,12 @@ GATE_CLOCKS(s3c6410_gate_clks) __initdata = { /* List of PLL clocks. */ static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = { - [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll", - APLL_LOCK, APLL_CON, NULL), - [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll", - MPLL_LOCK, MPLL_CON, NULL), - [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll", - EPLL_LOCK, EPLL_CON0, NULL), + PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll", + APLL_LOCK, APLL_CON, NULL), + PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll", + MPLL_LOCK, MPLL_CON, NULL), + PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll", + EPLL_LOCK, EPLL_CON0, NULL), }; /* Aliases for common s3c64xx clocks. */ diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index b6a436594a19..caf45cf7aa8e 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -147,6 +147,12 @@ static __init const char *exynos_get_domain_name(struct device_node *node) return kstrdup_const(name, GFP_KERNEL); } +static const char *soc_force_no_clk[] = { + "samsung,exynos5250-clock", + "samsung,exynos5420-clock", + "samsung,exynos5800-clock", +}; + static __init int exynos4_pm_init_power_domain(void) { struct device_node *np; @@ -183,6 +189,11 @@ static __init int exynos4_pm_init_power_domain(void) pd->pd.power_on = exynos_pd_power_on; pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; + for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++) + if (of_find_compatible_node(NULL, NULL, + soc_force_no_clk[i])) + goto no_clk; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { char clk_name[8];