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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-27 12:57:53 +00:00
drm/amdgpu: Implement a new 64bit sequence memory driver
Developed a new driver which allocates a 64bit memory on each request in sequence order. At the moment, user queue fence memory is the main consumer of this seq64 driver. v2: Worked on review comments from Christian for the following modifications - Move driver name from "semaphore" to "seq64" - Remove unnecessary PT/PD mapping - Move enable_mes check into init/fini functions. v3: Worked on review comments from Christian - drop enable_mes check - use DECLARE_BITMAP for bit array - added kerneldoc for seq64 v4: Worked on review comments from Christian - Rename amdgpu_seq64_get name with amdgpu_seq64_alloc v5: Worked on review comments from Christian - Fix seq64 lockdep warning - move fpriv->seq64_va check into amdgpu_seq64_unmap() - make the function amdgpu_seq64_unmap() return as void. - reserve the buffers as not interruptible. v6: port to drm_exec (Alex) v7: disable for now (Arun) Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
e8c2d3e25b
commit
c8031019dc
6 changed files with 311 additions and 1 deletions
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@ -80,7 +80,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \
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amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
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amdgpu_fw_attestation.o amdgpu_securedisplay.o \
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amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
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amdgpu_ring_mux.o amdgpu_xcp.o
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amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o
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amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
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@ -109,6 +109,7 @@
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#include "amdgpu_mca.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_xcp.h"
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#include "amdgpu_seq64.h"
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#define MAX_GPU_INSTANCE 64
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@ -468,6 +469,7 @@ struct amdgpu_fpriv {
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struct amdgpu_vm vm;
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struct amdgpu_bo_va *prt_va;
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struct amdgpu_bo_va *csa_va;
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struct amdgpu_bo_va *seq64_va;
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struct mutex bo_list_lock;
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struct idr bo_list_handles;
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struct amdgpu_ctx_mgr ctx_mgr;
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@ -986,6 +988,9 @@ struct amdgpu_device {
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/* GDS */
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struct amdgpu_gds gds;
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/* for userq and VM fences */
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struct amdgpu_seq64 seq64;
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/* KFD */
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struct amdgpu_kfd_dev kfd;
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@ -2676,6 +2676,12 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
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goto init_failed;
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}
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}
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r = amdgpu_seq64_init(adev);
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if (r) {
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DRM_ERROR("allocate seq64 failed %d\n", r);
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goto init_failed;
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}
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}
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}
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@ -3138,6 +3144,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
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amdgpu_device_wb_fini(adev);
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amdgpu_device_mem_scratch_fini(adev);
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amdgpu_ib_pool_fini(adev);
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amdgpu_seq64_fini(adev);
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}
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r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
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@ -1428,6 +1428,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
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fpriv->csa_va = NULL;
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}
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amdgpu_seq64_unmap(adev, fpriv);
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pasid = fpriv->vm.pasid;
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pd = amdgpu_bo_ref(fpriv->vm.root.bo);
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if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
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247
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
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247
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
Normal file
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@ -0,0 +1,247 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_seq64.h"
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#include <drm/drm_exec.h>
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/**
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* DOC: amdgpu_seq64
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*
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* amdgpu_seq64 allocates a 64bit memory on each request in sequence order.
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* seq64 driver is required for user queue fence memory allocation, TLB
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* counters and VM updates. It has maximum count of 32768 64 bit slots.
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*/
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/**
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* amdgpu_seq64_map - Map the seq64 memory to VM
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*
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* @adev: amdgpu_device pointer
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* @vm: vm pointer
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* @bo_va: bo_va pointer
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* @seq64_addr: seq64 vaddr start address
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* @size: seq64 pool size
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*
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* Map the seq64 memory to the given VM.
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*
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* Returns:
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* 0 on success or a negative error code on failure
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*/
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int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo_va **bo_va, u64 seq64_addr,
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uint32_t size)
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{
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struct amdgpu_bo *bo;
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struct drm_exec exec;
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int r;
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bo = adev->seq64.sbo;
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if (!bo)
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return -EINVAL;
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drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
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drm_exec_until_all_locked(&exec) {
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r = amdgpu_vm_lock_pd(vm, &exec, 0);
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if (likely(!r))
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r = drm_exec_lock_obj(&exec, &bo->tbo.base);
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drm_exec_retry_on_contention(&exec);
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if (unlikely(r))
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goto error;
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}
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*bo_va = amdgpu_vm_bo_add(adev, vm, bo);
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if (!*bo_va) {
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r = -ENOMEM;
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goto error;
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}
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r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, size,
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AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
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AMDGPU_PTE_EXECUTABLE);
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if (r) {
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DRM_ERROR("failed to do bo_map on userq sem, err=%d\n", r);
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amdgpu_vm_bo_del(adev, *bo_va);
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goto error;
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}
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r = amdgpu_vm_bo_update(adev, *bo_va, false);
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if (r) {
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DRM_ERROR("failed to do vm_bo_update on userq sem\n");
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amdgpu_vm_bo_del(adev, *bo_va);
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goto error;
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}
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error:
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drm_exec_fini(&exec);
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return r;
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}
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/**
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* amdgpu_seq64_unmap - Unmap the seq64 memory
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*
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* @adev: amdgpu_device pointer
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* @fpriv: DRM file private
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*
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* Unmap the seq64 memory from the given VM.
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*/
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void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv)
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{
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struct amdgpu_vm *vm;
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struct amdgpu_bo *bo;
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struct drm_exec exec;
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int r;
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if (!fpriv->seq64_va)
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return;
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bo = adev->seq64.sbo;
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if (!bo)
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return;
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vm = &fpriv->vm;
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drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
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drm_exec_until_all_locked(&exec) {
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r = amdgpu_vm_lock_pd(vm, &exec, 0);
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if (likely(!r))
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r = drm_exec_lock_obj(&exec, &bo->tbo.base);
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drm_exec_retry_on_contention(&exec);
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if (unlikely(r))
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goto error;
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}
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amdgpu_vm_bo_del(adev, fpriv->seq64_va);
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fpriv->seq64_va = NULL;
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error:
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drm_exec_fini(&exec);
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}
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/**
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* amdgpu_seq64_alloc - Allocate a 64 bit memory
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*
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* @adev: amdgpu_device pointer
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* @gpu_addr: allocated gpu VA start address
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* @cpu_addr: allocated cpu VA start address
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*
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* Alloc a 64 bit memory from seq64 pool.
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*
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* Returns:
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* 0 on success or a negative error code on failure
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*/
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int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr,
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u64 **cpu_addr)
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{
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unsigned long bit_pos;
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u32 offset;
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bit_pos = find_first_zero_bit(adev->seq64.used, adev->seq64.num_sem);
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if (bit_pos < adev->seq64.num_sem) {
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__set_bit(bit_pos, adev->seq64.used);
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offset = bit_pos << 6; /* convert to qw offset */
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} else {
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return -EINVAL;
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}
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*gpu_addr = offset + AMDGPU_SEQ64_VADDR_START;
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*cpu_addr = offset + adev->seq64.cpu_base_addr;
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return 0;
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}
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/**
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* amdgpu_seq64_free - Free the given 64 bit memory
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*
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* @adev: amdgpu_device pointer
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* @gpu_addr: gpu start address to be freed
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*
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* Free the given 64 bit memory from seq64 pool.
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*
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*/
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void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr)
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{
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u32 offset;
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offset = gpu_addr - AMDGPU_SEQ64_VADDR_START;
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offset >>= 6;
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if (offset < adev->seq64.num_sem)
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__clear_bit(offset, adev->seq64.used);
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}
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/**
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* amdgpu_seq64_fini - Cleanup seq64 driver
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*
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* @adev: amdgpu_device pointer
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*
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* Free the memory space allocated for seq64.
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*
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*/
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void amdgpu_seq64_fini(struct amdgpu_device *adev)
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{
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amdgpu_bo_free_kernel(&adev->seq64.sbo,
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NULL,
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(void **)&adev->seq64.cpu_base_addr);
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}
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/**
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* amdgpu_seq64_init - Initialize seq64 driver
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate the required memory space for seq64.
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*
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* Returns:
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* 0 on success or a negative error code on failure
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*/
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int amdgpu_seq64_init(struct amdgpu_device *adev)
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{
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int r;
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if (adev->seq64.sbo)
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return 0;
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/*
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* AMDGPU_MAX_SEQ64_SLOTS * sizeof(u64) * 8 = AMDGPU_MAX_SEQ64_SLOTS
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* 64bit slots
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*/
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r = amdgpu_bo_create_kernel(adev, AMDGPU_SEQ64_SIZE,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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&adev->seq64.sbo, NULL,
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(void **)&adev->seq64.cpu_base_addr);
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if (r) {
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dev_warn(adev->dev, "(%d) create seq64 failed\n", r);
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return r;
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}
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memset(adev->seq64.cpu_base_addr, 0, AMDGPU_SEQ64_SIZE);
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adev->seq64.num_sem = AMDGPU_MAX_SEQ64_SLOTS;
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memset(&adev->seq64.used, 0, sizeof(adev->seq64.used));
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return 0;
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}
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49
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
Normal file
49
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
Normal file
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@ -0,0 +1,49 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_SEQ64_H__
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#define __AMDGPU_SEQ64_H__
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#define AMDGPU_SEQ64_SIZE (2ULL << 20)
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#define AMDGPU_MAX_SEQ64_SLOTS (AMDGPU_SEQ64_SIZE / (sizeof(u64) * 8))
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#define AMDGPU_SEQ64_VADDR_OFFSET 0x50000
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#define AMDGPU_SEQ64_VADDR_START (AMDGPU_VA_RESERVED_SIZE + AMDGPU_SEQ64_VADDR_OFFSET)
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struct amdgpu_seq64 {
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struct amdgpu_bo *sbo;
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u32 num_sem;
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u64 *cpu_base_addr;
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DECLARE_BITMAP(used, AMDGPU_MAX_SEQ64_SLOTS);
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};
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void amdgpu_seq64_fini(struct amdgpu_device *adev);
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int amdgpu_seq64_init(struct amdgpu_device *adev);
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int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64 **cpu_addr);
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void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);
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int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo_va **bo_va, u64 seq64_addr, uint32_t size);
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void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv);
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#endif
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